Protection of three dimensional transistor structures during gate stack etch
Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.
1. An apparatus comprising:
a transistor fin having a top surface and at least two sidewall surfaces, wherein the transistor fin includes a channel region;
an oxide layer on at least the portion of the top surface of the transistor fin that is over the channel region of the transistor fin;
a high-k gate dielectric layer over the channel region of the transistor fin and the oxide layer but not over at least a different portion of the transistor fin, leaving the different portion of the transistor fin exposed; and
a metal gate electrode over the high-k gate dielectric.
2. The apparatus of claim 1 , further comprising:
a polysilicon layer over the metal gate electrode.
3. The apparatus of claim 1 , wherein the high-k gate dielectric comprises at least one of hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, or lanthanum oxide.
4. The apparatus of claim 1 , wherein the metal gate electrode comprises at least one of a metal nitride, a metal carbide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or a conductive metal oxide.
5. The apparatus of claim 1 , wherein the oxide layer extends along the entire top surface of the transistor fin.
6. The apparatus of claim 1 , wherein the transistor fin is on the insulator layer of a silicon-on-insulator substrate.
7. The apparatus of claim 1 , wherein the metal gate electrode has a top surface that is entirely above the top surface of the transistor fin.
8. A method comprising:
forming a transistor fin having a top surface and at least two sidewall surfaces;
forming an oxide hard mask layer on only the top surface of the transistor fin;
forming a gate dielectric layer over the transistor fin and the oxide hard mask layer;
forming a metal gate electrode layer over the gate dielectric layer; and
etching a portion of the metal gate electrode layer and the gate dielectric layer to expose a region of the transistor fin and the oxide bard mask layer.
9. The method of claim 8 , wherein forming the oxide hard mask layer on only the top surface of the transistor fin comprises:
forming sidewall spacers adjacent to at least a portion of the sidewalls of the transistor fin;
oxidizing only the top surface of the transistor fin to form the oxide layer; and
removing the sidewall spacers.
10. The method of claim 8 , wherein the gate dielectric layer comprises a high-k gate dielectric material.
11. The method of claim 8 , wherein the metal gate electrode layer comprises at least one of a metal nitride, a metal carbide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt nickel or a conductive metal oxide.
12. The method of claim 8 , wherein forming the transistor fin comprises patterning and etching a silicon layer of a silicon-on insulator substrate.
13. The method of claim 9 , wherein forming the sidewall spacers comprises:
forming a conformal nitride layer over the transistor fin; and
anisotropically etching the conformal nitride layer to remove the nitride layer from the top surface of the transistor fin.
14. The method of claim 10 , wherein the high-k gate dielectric material comprises at least one of hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, or lanthanum oxide.
15. A method comprising:
forming a transistor fin having a top surface and at least two sidewall surfaces;
forming a conformal layer over the transistor fin;
etching the conformal layer to form sidewall spacers adjacent to at least part of the sidewall surfaces of the transistor fin;
forming a hard mask layer on only the top surface of the transistor fin after forming the sidewall spacers;
removing the sidewall spacers after forming the hard mask layer;
forming a gate dielectric layer over the transistor fin and the hard mask layer;
forming a gate electrode layer over the gate dielectric layer; and
etching a portion of the gate electrode layer and the gate dielectric layer to expose a region of transistor fin.
16. The method of claim 15 , wherein the sidewall spacers prevent the hard mask layer from forming on the sidewall surfaces of the transistor fin during forming the hard mask layer.
17. The method of claim 15 , wherein the gate dielectric layer comprises a high-k gate dielectric material.
18. The method of claim 15 , wherein the gate electrode layer comprises a metal.
19. The method of claim 15 , wherein the sidewall spacers comprise a nitride material.
20. The method of claim 15 , wherein the transistor fin comprises silicon and the hard mask layer comprises an oxide.
21. The method of claim 15 , further comprising:
removing a portion of the top of the transistor fin after forming the sidewall spacers to recess the top surface of the transistor fin below the sidewall spacers.
22. The method of claim 15 , further comprising:
forming a polysilicon layer over the metal gate electrode layer; and
etching a portion of the polysilicon layer to expose the portion of the gate electrode layer.
23. The method of claim 18 , wherein the gate electrode layer comprises at least one of a metal nitride, a metal carbide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or a conductive metal oxide.