IP Library › Granted Patent US 7,522,397
Granted Patent B2
US 7,522,397 · App. 11/506,157 · Granted Apr 21, 2009

Input/output interface with current sensing

Assignee: Infineon Technologies AG
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Quick Facts
Patent No.
US 7,522,397
App. No.
11/506,157
Granted
Apr 21, 2009
Kind
B2
Abstract

An interface circuit includes an input terminal, a controlled current sink, a current measurement arrangement, and a logic circuit. The input terminal is configured to receive an input signal. The controlled current sink is operably coupled to the input terminal, and is operable to controllably take up a current from the input terminal according to a transmission signal. The current measurement arrangement is configured to generate a current measurement signal based on the current taken up by the current sink. The logic circuit is operably coupled to receive the current measurement signal and the input signal, and is configured to generate a signal depending on the input signal.

Claims (31)

1. Interface circuit, comprising:

an input terminal configured to provide an input signal and receive information present in the input signal,

a controlled current sink operably coupled to the input terminal, the controlled current sink operable to controllably take up a current from the input terminal according to a transmission signal for providing information via the input terminal,

a current measurement arrangement configured to generate a current measurement signal based on the current taken up by the current sink,

a logic circuit operably coupled to receive the current measurement signal and the input signal, the logic circuit configured to generate a signal depending on the input signal.

2. The interface circuit according to claim 1 , wherein the current measurement arrangement comprises

a measuring resistor connected in series with the current sink,

a comparison arrangement configured to generate the current measurement signal based on a comparison of a voltage present across the measuring resistor and a reference value.

3. The interface circuit according to claim 1 , wherein the current sink comprises a current source and a switch connected in series with the current source, the switch controllably actuated responsive to the transmission signal.

4. The interface circuit according to claim 1 , wherein the logic circuit comprises an OR gate, the OR gate operable to perform an OR operation on with the input signal and the current measurement signal.

5. The interface circuit according to claim 1 , wherein the input terminal includes further comprises a buffer configured to generate the input signal from an external input signal.

6. An interface circuit, comprising:

a controlled current sink operably coupled to receive a first input signal, the controlled current sink operable to controllably take up a current from the first input signal according to a transmission signal for providing information via an input terminal,

a current measurement arrangement configured to generate a current measurement signal based on the current taken up by the current sink,

a logic circuit operably coupled to receive the current measurement signal and a second input signal, the second input signal representative of the first input signal, the logic circuit configured to generate an output signal depending on the second input signal and the current measurement signal.

7. The interface circuit according to claim 6 , wherein the current measurement arrangement comprises

a measuring resistor connected in series with the current sink,

a comparison arrangement configured to generate the current measurement signal based on a comparison of a voltage present across the measuring resistor and a reference value.

8. The interface circuit according to claim 6 , wherein the current sink comprises a current source and a switch connected in series with the current source, the switch controllably actuated responsive to the transmission signal.

9. The interface circuit according to claim 6 , wherein the logic circuit comprises an OR gate, the OR gate operable to perform an OR operation on with the second input signal and the current measurement signal.

10. The interface circuit according to claim 6 , wherein the input terminal includes further comprises a buffer configured to generate the second input signal based on the first input signal.

11. The interface circuit according to claim 6 , wherein the current measurement arrangement comprises

a measuring resistor connected in series with the current sink,

an arrangement configured to provide the current measurement signal based on a voltage present across the measuring resistor.

12. The interface circuit according to claim 11 , wherein the arrangement comprises a comparator.

13. The interface circuit according to claim 11 , wherein the current sink comprises a current source and a switch connected in series with the current source, the switch controllably actuated responsive to the transmission signal.

14. The interface circuit according to claim 11 , wherein the logic circuit comprises an OR gate, the OR gate operable to perform an OR operation on with the second input signal and the current measurement signal.

15. The interface circuit according to claim 11 , wherein the input terminal includes further comprises a buffer configured to generate the second input signal based on the first input signal.

16. The interface circuit according to claim 12 , wherein the current sink comprises a current source and a switch connected in series with the current source, the switch controllably actuated responsive to the transmission signal.

17. The interface circuit according to claim 16 , wherein the logic circuit comprises an OR gate, the OR gate operable to perform an OR operation on with the second input signal and the current measurement signal.

18. The interface circuit according to claim 17 , wherein the input terminal includes further comprises a buffer configured to generate the second input signal based on the first input signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2006
From: FILIPPO, ROBERTO; CORTIGIANI, FABRIZIO; MIGNOLI, FRANCO; SOLDA, SILVIA
To: INFINEON TECHNOLOGIES AG
Reel/Frame 018511/0225 →
Priority Claims (1)
EP 05017780 · Aug 16, 2005 · regional
Continuity (1)
Related Publication 20070040578A1 · Feb 22, 2007