Online initial mirror synchronization and mirror synchronization verification in storage area networks
Systems and methods in accordance with various disclosed embodiments can manage a mirrored virtual target to synchronize the members of the virtual target and/or to verify that the members of the virtual target are synchronized. In one embodiment, a mirrored virtual target is synchronized by first provisioning at least one first internal virtual logical unit (IVLU) corresponding to at least one destination target of the mirrored target and a second IVLU corresponding to a source target of the mirrored target. A write command is first issued, via one or more internal virtual logical units, to each of the destination target members of the mirrored target. When each destination target is available to receive data, as evidenced by a returned transfer ready signal, a read command is provided to the source target via the second internal virtual logical unit. In this manner, a data path between the source and destination targets is established prior to reading data from the source target. Accordingly, the data can be read from the source target, converted to write data, and routed to the destination targets at line speed without buffering of the data. A similar process is provided to verify that the members of a mirrored target are synchronized. In one embodiment, a system and method is provided to manage incoming commands for the mirrored target while synchronizing or verifying synchronization of the mirrored target. Incoming commands can be queued as they are received and provided to the mirrored target when pending synchronization or verification commands are completed.
1. A method performed by a storage switch which routes data between a plurality of initiators and targets in a storage network for managing a mirrored target comprising a source target and at least one destination target, the method comprising:
determining by the switch an availability of said at least one destination target to receive data by providing one of a write command or a verify command to said at least one destination target;
providing by the switch a read command to said source target only when said at least one destination target is determined to be available to receive data;
receiving by the switch read data from said source target in response to said read command;
converting by the switch said read data to write data or verify data without buffering said read data or said write data or verify data;
transferring the switch said write data or verify data to said at least one destination target without buffering the write data or verify data; and
provisioning by the switch a first internal virtual logical unit corresponding to said at least one destination target and a second internal virtual logical unit corresponding to said source target to pre-establish an internal data flow through the switch to facilitate said transferring of data without buffering from said source target to said at least one destination target.
2. The method of claim 1 , wherein said step of determining an availability comprises
determining whether said at least one destination target returns a transfer ready signal in response to said write command or said verify command.
3. The method of claim 1 , wherein said at least one destination target comprises first and second destination targets, and wherein:
said step of provisioning a first internal virtual logical unit comprises provisioning the first internal virtual logical unit corresponding to the first destination target; and
said method further comprises provisioning a third internal virtual logical unit corresponding to the second destination target.
4. The method of claim 1 wherein:
said step of provisioning a first internal virtual logical unit comprises provisioning a first member of said first internal virtual logical unit that corresponds to a first destination target and a second member that corresponds to a second destination target.
5. The method of claim 1 , wherein said step of determining an availability comprises:
providing said write or verify command to a processing unit in the switch associated with said first internal virtual logical unit;
determining by the processing unit a location of said at least one destination target from information provisioned for said first internal virtual logical unit;
providing said write or verify command to said at least one destination target from said processing unit; and
determining by the processing unit whether said at least one destination target returns a transfer ready signal.
6. The method of claim 5 , wherein:
said processing unit is a first processing unit; and
said switch includes a second processing unit, said second processing unit operating as an internal initiator in the switch that provides said first write or verify command to said first processing unit and determines whether said at least one destination target returns a transfer ready signal.
7. The method of claim 6 , wherein said step of providing a read command comprises:
providing a read command from said second processing unit to said second internal virtual logical unit when said at least one destination target returns said transfer ready signal; and
routing said read command from said first processing unit to said source target using information provisioned for said second internal virtual logical unit.
8. The method of claim 1 , wherein said switch has a plurality of processing units, each being associated with one or more targets and each having an ingress portion and an egress portion for data, and wherein said converting said read data comprises:
receiving said read data at an egress portion of a first processing unit associated with said source target;
converting said read data to said write data or verify data at said egress portion of said first processing unit; and
routing said write data or verify data from said egress portion to an ingress portion of said first processing unit; and wherein
said transferring comprises routing said write data or verify data from said ingress portion to said at least one destination target.
9. The method of claim 8 , wherein:
said read data is one or more read data packets;
said step of converting said read data to write data or verify data at said egress portion of said first processing unit includes updating header information of said one or more read data packets to indicate that said one or more read data packets are one or more write data or verify data packets.
10. The method of claim 6 , wherein said command is a verify command, said method further comprising:
converting said read data to verify data; and
transferring said verify data to said at least one destination target;
and the method further comprises comprising said verify data with data stored at said at least one destination target to verify that said verify data and said stored data are the same.
11. The method of claim 10 , wherein converting said read data comprises:
receiving said read data at an egress portion of said first processing unit;
converting said read data to said verify data at said egress portion of said first processing unit;
routing said verify data from said egress portion to an ingress portion of said first processing unit; and
routing said verify data from said ingress portion to said at least one destination target.
12. The method of claim 11 , wherein:
said read data is one or more read data packets; and
said step of converting said read data to verify data at said egress portion of said first processing unit includes updating header information of said one or more read data packets to indicate that said one or more read data packets are one or more verify data packets.
13. The method of claim 5 , wherein:
said processing unit is a first processing unit; and
said step of providing said write or verify command to said at least one destination target includes providing said write or verify command to a second processing unit in communication with said at least one destination target.
14. The method of claim 1 , further comprising:
receiving an initiator provided command for said mirrored target while a synchronization or verification command for said mirrored target is pending;
queuing said initiator provided command;
dequeuing and providing said initiator provided command to said mirrored target when said synchronization or said verification command is complete.
15. The method of claim 14 , wherein:
said steps of receiving, queuing, and dequeuing are performed without said initiator experiencing a loss of service of said mirrored target.
16. The method of claim 1 wherein:
said step of converting read data to write data or verify data is performed at line speed.
17. Storage Switch apparatus to manage a mirrored target including at least one destination target and a source target in a storage network that includes a plurality of initiators and targets, comprising:
at least one port in communication with said at least one destination target and said source target;
at least one processing unit in communication with said at least one port, said at least one processing unit determines the availability of said at least one destination target to receive data by providing one of a write command or a verify command to said at least one destination target, and said at least one processing unit further provides a read command to said source target only when said at least one destination target is available to receive data, receives and converts read data from said source target to write data or verify data without buffering said read data or said write data or verify data, and transfers said write data or verify data to said at least one destination target without buffering the write data or verify data; and
a memory in communication with said at least one processing unit, said at least one processing unit provisions in said memory a first internal virtual logical unit corresponding to said at least one destination target and a second internal virtual logical unit corresponding to said source target, said first and second internal virtual logical units establishing an internal data flow through the switch prior to receiving data to facilitate said transfer of the write or verify data without buffering.
18. The apparatus of claim 17 , wherein:
said at least one processing unit determines said availability by determining whether said at least one destination target returns a transfer ready signal in response to said write or a verify command.
19. The apparatus of claim 17 , wherein:
said first internal virtual logical unit corresponds to a first destination target; and
said memory further includes a third internal virtual logical unit corresponding to a second destination target.
20. The apparatus of claim 17 , wherein:
said first internal virtual logical unit includes a first member corresponding to a first destination target and a second member corresponding to a second destination target.
21. The apparatus of claim 17 , wherein:
said at least one processing unit includes a first processing unit and a second processing unit, said first processing unit is associated with said first and second internal virtual logical units.
22. The apparatus of claim 21 , wherein:
said second processing unit provides said write command or verify command to said first processing unit, said write command or verify command is for said first internal virtual logical unit;
said first processing unit determines a location of said at least one destination target from information provisioned for said first internal virtual logical unit in said memory;
said first processing unit provides said write command or verify command to said at least one destination target after determining said location; and
said second processing unit determines whether said at least one destination target returns said transfer ready signal.
23. The apparatus of claim 22 , wherein:
said second processing unit provides said read command to said first processing unit when said at least one destination target returns said transfer ready signal, said read command is for said second internal virtual logical unit; and
said first processing unit routes said read command to said source target using information provisioned for said second internal virtual logical unit.
24. The apparatus of claim 23 , wherein said switch comprises a plurality of linecards, each having a plurality of ports in communication with source or destination targets, and wherein said information identifies a linecard and port to which said destination target is coupled.
25. The apparatus of claim 23 , wherein:
said write command or verify command is a write command;
said first processing unit receives said read data from said source target after providing said read command, said first processing unit converts said read data to said write data and provides said write data to said at least one destination target.
26. The apparatus of claim 25 , wherein:
said first processing unit includes an ingress portion and an egress portion, said first processing unit receives said read data and converts said read data to said write data at said egress portion, said write data is routed from said egress portion to said ingress portion, said write data is routed from said ingress portion to said at least one destination target.
27. The apparatus of claim 26 , wherein:
said read data is one or more read data packets; and
said first processing unit converts said read data to said write data by updating header information of said one or more read data packets to indicate that said one or more read data packets are one or more write data packets.
28. The apparatus of claim 23 , wherein:
said write command or verify command is a verify command; and
said first processing unit receives read data from said source target after providing said read command, said first processing unit converts said read data to verify data and provides said verify data to said at least one destination target.
29. The apparatus of claim 28 , wherein:
said first processing unit includes an ingress portion and an egress portion, said first processing unit receives said read data and converts said read data to said verify data at said egress portion, said verify data is routed from said egress portion to said ingress portion, said verify data is routed from said ingress portion to said at least one destination target.
30. The apparatus of claim 29 , wherein:
said read data is one or more read data packets; and
said first processing unit converts said read data to said verify data by updating header information of said one or more read data packets to indicate that said one or more read data packets are one or more verify data packets.
31. The apparatus of claim 22 , wherein:
said first processing unit provides said first command to said at least one destination target by providing said first command to a third processing unit in communication with said at least one destination target, said third processing unit routes said first command to said at least one destination target.
32. The apparatus of claim 25 , wherein:
said first processing unit is capable of converting said read data to said write data at line speed.
33. The apparatus of claim 28 , wherein:
said first processing unit is capable of converting said read data to said verify data at line speed.
34. The apparatus of claim 28 , wherein:
said first processing unit is capable of converting said read data to said verify data without buffering said read data or said verify data.
35. The apparatus of claim 21 , wherein:
said first processing unit is in communication with said at least one destination target.
36. The apparatus of claim 21 , wherein:
said first processing unit is in communication with said source target.
37. The apparatus of claim 21 , wherein:
said first processing unit is not a processing unit for a port in communication with said at least one destination target or said source target.
38. The apparatus of claim 17 , further comprising:
a memory, said at least one processing unit queues incoming commands for said mirrored target in said memory while said apparatus is processing a synchronization or verification command for said mirrored target, said at least one processing unit dequeues and provides said incoming commands to said mirrored target when said synchronization or verification command is complete.
39. The apparatus of claim 38 , wherein:
said incoming commands are received from at least one initiator; and
said at least one processing unit queues said incoming commands without said apparatus providing a failure response to said at least one initiator.
40. The apparatus of claim 39 , wherein:
said failure response includes a busy response and a task set full response.
41. The apparatus of claim 39 , wherein:
said at least one processing unit queues, dequeues, and provides said incoming commands without said at least one processing unit experiencing a loss of service of said mirrored target.
42. The apparatus of claim 17 , wherein:
said mirrored target is a mirrored virtual logical unit.
43. One or more processor readable storage devices having processor readable code embodied thereon, said processor readable code for programming one or more processors in a storage switch to control the operation of the storage switch to perform a method comprising:
determining an availability of at least one destination target to receive data by providing one of a write command or a verify command to said at least one destination target;
providing a read command to a source target only when said at least one destination target is determined to be available to receive data;
receiving read data from said source target in response to said read command;
converting said read data to write data or verify data without buffering said read data or said write data or verify data;
transferring said write data or verify data to said at least one destination target without buffering the write data or verify data; and
provisioning a first internal virtual logical unit corresponding to said at least one destination target and a second internal virtual logical unit corresponding to said source target to pre-establish an internal data flow through the switch to facilitate said transferring of data without buffering from said source target to said at least one destination target.
44. One or more processor readable storage devices according to claim 43 , wherein:
said step of converting said read data to write data or verify data is performed at line speed.
45. One or more processor readable storage devices according to claim 43 , wherein said at least one destination target comprises first and second destination targets, and wherein said step of provisioning the first internal virtual logical unit comprises provisioning the first internal virtual logical unit corresponding to the first destination target; and the switch further provisions a third internal virtual logical unit corresponding to the second destination target.