Precision sampling circuit

1. A The sampling circuit comprising:

an input voltage source;

a first switch having an input operatively connected to said input voltage source;

a first capacitor operatively connected to an output of said first switch;

a second switch having an input operatively connected to said first capacitor;

a second input voltage source;

a third switch having an input operatively connected to said second input voltage source;

a second capacitor operatively connected to an output of said third switch;

a fourth switch having an input operatively connected to said second capacitor; and

a third capacitor being operatively connected across said output of said third switch and said output of said first switch.

2. The sampling circuit as claimed in claim 1 , wherein said third switch has a variable parasitic capacitance and said third capacitor has a capacitance greater than the variable parasitic capacitance of said third switch.

3. The sampling circuit as claimed in claim 1 , wherein said third switch has a variable parasitic capacitance and a combined variable parasitic capacitance of said third switch and capacitance of said third capacitor is more linear than the variable parasitic capacitance of said third switch.

4. The sampling circuit as claimed in claim 1 , further comprising a first buffer amplifier operatively connected between said first input voltage source and a back-gate of said first switch.

5. The sampling circuit as claimed in claim 1 , further comprising a first amplifier operatively connected to a gate of said first switch to bias the gate of said first switch at a voltage that is offset by a constant amount from an input voltage of said first input voltage source.

6. The sampling circuit as claimed in claim 1 , further comprising:

a first buffer amplifier operatively connected between said first input voltage source and a back-gate of said first switch; and

a second buffer amplifier operatively connected between said second input voltage source and a back-gate of said third switch.

7. The sampling circuit as claimed in claim 6 , further comprising:

a first amplifier operatively connected to a gate of said first switch to bias the gate of said first switch at a voltage that is offset by a constant amount from an input voltage of said first input voltage source; and

a second amplifier operatively connected to a gate of said third switch to bias the gate of said third switch at a voltage that is offset by a constant amount from an input voltage of said second input voltage source.

8. A sampling circuit comprising:

an input voltage source;

a first switch having an input operatively connected to said input voltage source;

a first capacitor operatively connected to an output of said first switch;

a differential amplifier having an inverting input operatively connected to said first capacitor;

a second switch operatively connected across the inverting input of said differential amplifier and a non-inverting output of said differential amplifier;

a second input voltage source;

a third switch having an input operatively connected to said second input voltage source;

a second capacitor operatively connected to an output of said third switch;

a fourth switch operatively connected across a non-inverting input of said differential amplifier and an inverting output of said differential amplifier; and

a third capacitor being operatively connected across said output of said third switch and said output of said first switch.

9. The sampling circuit as claimed in claim 8 , wherein said third switch has a variable parasitic capacitance and said third capacitor has a capacitance greater than the variable parasitic capacitance of said third switch.

10. The sampling circuit as claimed in claim 8 , wherein said third switch has a variable parasitic capacitance and a combined variable parasitic capacitance of said third switch and capacitance of said third capacitor is more linear than the variable parasitic capacitance of said third switch.

11. The sampling circuit as claimed in claim 8 , further comprising:

a first buffer amplifier operatively connected between said first input voltage source and a back-gate of said first switch; and

a second buffer amplifier operatively connected between said second input voltage source and a back-gate of said third switch.

12. The sampling circuit as claimed in claim 11 , further comprising:

a first amplifier operatively connected to a gate of said first switch to bias the gate of said first switch at a voltage that is offset by a constant amount from an input voltage of said first input voltage source; and

a second amplifier operatively connected to a gate of said third switch to bias the gate of said third switch at a voltage that is offset by a constant amount from an input voltage of said second input voltage source.

13. The sampling circuit as claimed in claim 8 , further comprising:

a first buffer amplifier operatively connected between said first input voltage source and a back-gate of said first switch; and

a second buffer amplifier operatively connected between said second input voltage source and a back-gate of said third switch.

14. The sampling circuit as claimed in claim 13 , further comprising:

a first amplifier operatively connected to said gate of said first switch to bias the gate of said first switch at a voltage that is offset by a constant amount from an input voltage of said first input voltage source; and

a second amplifier operatively connected to said gate of said third switch to bias the gate of said third switch at a voltage that is offset by a constant amount from an input voltage of said second input voltage source.