IP Library › Granted Patent US 7,535,765
Granted Patent B2
US 7,535,765 · App. 11/822,777 · Granted May 19, 2009

Non-volatile memory device and method for reading cells

Assignee: Saifun Semiconductors Ltd.
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Quick Facts
Patent No.
US 7,535,765
App. No.
11/822,777
Filed
Jul 10, 2007
Granted
May 19, 2009
Kind
B2
Examiner
LE, VU ANH
Art Unit
2824
USPC
365/185.2
Abstract

A non-volatile device and method of operating the device including changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step may include determining a history read reference level of a history cell associated with a group of memory cells of a non-volatile memory cell array and comparing sensed logical state distributions with stored logical state distributions.

Claims (21)

1. A method for selecting a read reference level associated with a given logical state for a set of non-volatile memory (“NVM”) cells, said method comprising:

deriving an initial read reference level from a history cell associated with the set of NVM cells; and

comparing logical state distribution of the set of NVM cells sensed using the initial read reference level against a stored logical state distribution of the set of NVM cells.

2. The method according to claim 1 , wherein deriving an initial read reference level comprises determining a reference level for the history cell.

3. The method according to claim 2 , wherein the initial read reference level associated with a given logical state for a set of NVM cells is at a level not equal to the reference level of the history cell from which it is derived.

4. The method according to claim 3 , wherein a difference between the initial read reference level associated with a given logical state for a set of NVM cells and the reference level for the history cell from which it is derived is based on a predetermined margin to be maintained.

5. The method according to claim 2 , wherein the initial read reference level associated with a given logical state for a set of NVM cells is at a level substantially equal to the read reference level of the history cell from which it is derived.

6. The method according to claim 1 further comprising adjusting the initial read reference level based on results of the comparison of logical state distributions.

7. The method according to claim 2 , wherein the initial read reference level is adjusted upward if the number of NVM cells sensed at a given logical state is higher than a stored value.

8. The method according to claim 2 , wherein the initial read reference level is adjusted downward if the number of cells sensed at a given logical state is lower than a stored value.

9. An non-volatile memory (“NVM”) device comprising:

an NVM array including a set of non-volatile memory (“NVM”) cells; and

control logic adapted derive an initial read reference level from a history cell associated with the set of NVM cells; and

to compare logical state distribution of the set of NVM cells sensed using the initial read reference level against a stored logical state distribution of the set of NVM cells.

10. The device according to claim 9 , wherein the control logic is adapted to derive an initial read reference level by determining a reference level for the history cell.

11. The device according to claim 10 , wherein the initial read reference level associated with a given logical state for a set of NVM cells is at a level not equal to the reference level of the history cell from which it is derived.

12. The device according to claim 11 , wherein a difference between the initial read reference level associated with a given logical state for a set of NVM cells and the reference level for the history cell from which it is derived is based on a predetermined margin to be maintained.

13. The device according to claim 10 , wherein the initial read reference level associated with a given logical state for a set of NVM cells is at a level substantially equal to the reference level of the history cell from which it is derived.

14. The device according to claim 9 , wherein said control logic is further adapted to adjust the initial read reference level based on results of the comparison of logical state distributions.

15. The device according to claim 10 , wherein the initial read reference level is adjusted upward if the number of NVM cells sensed at a given logical state is higher than a stored value.

16. The device according to claim 10 , wherein the initial read reference level is adjusted downward if the number of cells sensed at a given logical state is lower than a stored value.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FOLLOWING NUMBERS 6272046,7277824,7282374,7286384,7299106,7337032,7460920,7519447 PREVIOUSLY RECORDED ON REEL 039676 FRAME 0237. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 16, 2018
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING
Reel/Frame 047797/0854 →
SECURITY INTEREST Recorded Aug 15, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039676/0237 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2007
From: MAAYAN, EDUARDO
To: SAIFUN SEMICONDUCTORS LTD
Reel/Frame 019776/0445 →
Continuity (3)
Continuation In Part 1120541100 · Aug 17, 2005
Continuation In Part 1100733200 · Dec 9, 2004
Related Publication 20080002464A1 · Jan 3, 2008