Standard cell, standard cell library, and semiconductor integrated circuit with suppressed variation in characteristics
In a standard cell, at least one of transistors on either side of a transistor having gate length different from that of the other transistors are set to be always in the OFF state. This prevents influence to the operation of the standard cell even with variation in final gate dimension, suppressing variation in characteristics of the standard cell.
1. A standard cell having a rectangular shape defined by a first direction and a second direction that is perpendicular to the first direction, the standard cell comprising:
a plurality of transistors each having a diffusion region and a gate,
a power supply wiring extended in the first direction,
wherein the plurality of transistors include:
at least one first transistor having larger gate length than the other transistors; and
at least one second transistor adjacent to the first transistor and having a diffusion region apart from a diffusion region of the first transistor, and
wherein the gate length of the at least one first transistor is defined by a length of gate in the first direction, and
wherein a dummy gate is provided between the first transistor and the second transistor,
a source/drain of the first transistor and a source/drain of the second transistor are separated;
a width of the dummy gate in the first direction is smaller than a distance between the source/drain of the first transistor and the source/drain of the second transistor; and
the dummy gate is provided in a region between the first and second transistors when viewed in plan view.
2. The standard cell of claim 1 , wherein
the first transistor has the second transistor on both adjacent sides.
3. The standard cell of claim 1 , wherein
the gates of the plurality of transistors and the dummy gate are arranged at regular intervals.
4. The standard cell of claim 1 , wherein the at least one first transistor includes an n-type first transistor and a p-type first transistor.
5. The standard cell of claim 4 ,
wherein the at least one second transistor includes an n-type second transistor and a p-type second transistor,
wherein a first dummy gate is provided between the n-type first transistor and the n-type second transistor, and
wherein a second dummy gate is provided between the p-type first transistor and the p-type second transistor.
6. The standard cell of claim 4 , wherein the n-type first transistor is opposed to the p-type first transistor.
7. The standard cell of claim 1 , wherein the number of the at least one first transistor is more than two.
8. The standard cell of claim 7 , wherein the dummy gate is provided adjacent to each one of the first transistors.
9. A standard cell library comprising at least one standard cell according to claim 1 .
10. A semiconductor integrated circuit comprising at least one standard cell according to claim 1 .
11. A standard cell library comprising a plurality of standard cells including a plurality of transistors each having a diffusion region and a gate,
wherein among the plurality of standard cell, any standard cell including a transistor having larger gate length than the other transistors is the standard cell of claim 1 .
12. A semiconductor integrated circuit comprising a plurality of standard cells including a plurality of transistors each having a diffusion region and a gate,
wherein among the plurality of standard cell, any standard cell including a transistor having larger gate length than the other transistors is the standard cell of claim 1 .