Capacitorless DRAM on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.
1. A system, comprising:
a silicon substrate;
an insulator layer positioned over a portion of the silicon substrate;
a localized silicon-over-insulator layer positioned over and laterally surrounded by the insulator layer;
a semiconductor stud extending through the insulator layer from the silicon substrate to the silicon-over-insulator layer;
a source;
a first drain and a second drain;
a first floating body formed between the source and the first drain, and a second floating body formed between the source and the second drain, the floating bodies defined within the localized silicon-over-insulator layer, wherein the insulator surrounds the source; and
a first gate adjacent the first floating body, and a second gate adjacent the second floating body.
2. The system of claim 1 ,
wherein the first and second floating bodies are redundant.
3. The system of claim 2 , wherein the source is configured to conduct a current having values indicative of three states, the three states comprising:
a first state, in which the first and second floating bodies store a “0” bit;
a second state, in which one of the first and second floating bodies stores a “0” bit, and the other of the first and second floating bodies stores a “1” bit; and
a third state, in which the first and second floating bodies store a “1” bit, and wherein the second and third states are not differentiated upon detection of the current.
4. The system of claim 3 , wherein the first floating body is configured to attain the first state when the first drain is placed at a first elevated voltage relative to the first gate.
5. The system of claim 4 , wherein the first floating body is configured to attain the second state when the first gate is placed at a second elevated voltage relative to the first drain.
6. The system of claim 5 , wherein the first state causes an increased source current at the source, and the second state causes a decreased source current at the source.
7. The system of claim 2 , wherein the floating bodies operate by gate-induced drain leakage currents.
8. The system of claim 1 , wherein the source is configured to conduct a current having values indicative of three states, the three states comprising:
a first state, in which the first and second floating bodies store a “0” bit;
a second state, in which one of the first and second floating bodies stores a “0” bit, and the other of the first and second floating bodies stores a “1” bit; and
a third state, in which the first and second floating bodies store a “1” bit, and wherein the second and third states are not differentiated upon detection of the current.
9. The system of claim 8 , wherein the first floating body is configured to attain the first state when the first drain is placed at a first elevated voltage relative to the first gate.
10. The system of claim 9 , wherein the first floating body is configured to attain the second state when the first gate is placed at a second elevated voltage relative to the first drain.
11. The system of claim 10 , wherein the first state causes an increased source current at the source, and the second state causes a decreased source current at the source.
12. The system of claim 8 , wherein the floating bodies operate by gate-induced drain leakage currents.
13. The system of claim 8 , wherein the second floating body is configured to attain the first state when the second drain is placed at a first elevated voltage relative to the second gate.
14. The system of claim 13 , wherein the second floating body is configured to attain the second state when the second gate is placed at a second elevated voltage relative to the second drain.
15. The system of claim 14 , wherein the first state causes an increased source current at the source, and the second state causes a decreased source current at the source.