Reflectometry test system using a sliding pseudo-noise reference
A technique for reflectometry testing of a signal path is disclosed. The technique includes injecting a test signal based on a probe pseudo-noise sequence into the signal path and obtaining a response signal. A sliding reference pseudo-noise sequence is correlated against the response signal. Both the probe sequence and the reference sequence are generated at a chip rate. The correlation is obtained for integer chip time delays, and sub-chip resolution of a peak correlation delay is estimated from at least two samples of the correlation.
1. A system for reflectometry testing of a signal path, comprising:
a system clock configured to output a clock at a chip rate;
a pseudo-noise generator coupled to the system clock and configured to output a probe sequence of pseudo-random chips at the chip rate, wherein the sequence repeats every L chips;
a sliding pseudo-noise generator coupled to the system clock and configured to output a reference sequence at the chip rate, wherein the reference sequence repeats every L+1 chips and the reference sequence is equal to the probe sequence over a continuous segment of length L chips;
a signal path interface coupled to the pseudo-noise generator and configured to inject the probe sequence into the signal path and obtain a resulting response signal from the signal path;
a correlator coupled to the signal path interface and the sliding pseudo-noise generator and configured to determine a correlation of the response signal and the reference sequence and output samples of the correlation at intervals of L+1 chips; and
an estimator coupled to the correlator and configured to estimate a peak correlation delay time from at least two of the samples of the correlation, wherein the peak correlation delay time includes an integer chip number portion and a fractional chip number portion.
2. The system of claim 1 wherein the pseudo-noise generator, sliding pseudo-noise generator, correlator, and estimator are all implemented on a monolithic integrated circuit.
3. The system of claim 1 wherein the system is integrated into an operational system.
4. The system of claim 1 wherein the correlator and estimator operate at the chip rate.
5. The system of claim 1 wherein the pseudo-noise generator comprises a linear feedback shift register.
6. The system of claim 1 wherein the signal path interface comprises a signal coupler selected from the group consisting of a direct connection, a series connected capacitor, a series connected inductor, a capacitive coupler, an inductive coupler, and a directional coupler.
7. The system of claim 1 wherein the signal path interface comprises an injection portion and an extraction portion.
8. The system of claim 1 wherein the signal path interface comprises a modulator configured to modulate the probe pseudo-noise sequence by carrier frequency prior to injection into the signal path.
9. The system of claim 8 wherein the signal path interface comprises a demodulator configured to demodulate the response signal before correlation with the reference pseudo-noise sequence.
10. The system of claim 8 wherein the sliding pseudo-noise generator comprises a modulator configured to modulate the reference pseudo-noise sequence by the carrier frequency before correlation with the resulting response signal.
11. The system of claim 1 wherein the response signal includes a superimposed operational signal present within the signal path.
12. The system of claim 1 wherein the correlator comprises:
a mixer configured to multiply the response signal and the reference pseudo-noise sequence to form a product; and
a filter coupled to the mixer and configured to filter the product and output the correlation.
13. The system of claim 12 wherein the mixer is a Gilbert-cell mixer.
14. The system of claim 12 wherein the filter is a Gm-C filter.
15. The system of claim 12 wherein the filer is a passive RC filter.
16. The system of claim 1 wherein the estimator comprises a linear interpolator configured to determine a fractional chip number portion of the peak correlation delay time from an extremum correlation value and an adjacent correlation value offset from the extremum correlation value by a one chip delay.
17. The system of claim 1 wherein the estimator comprises an interpolator matched to the correlation pulse shape.
18. A system for reflectometry testing of a signal path, comprising:
means for generating a probe sequence at a chip rate, the probe sequence being a pseudo-noise sequence which repeats every L chips;
means for generating a reference pseudo-noise sequence at the chip rate, the reference pseudo-noise sequence being equal to the probe pseudo-noise sequence over a segment of length L chips and repeating every L+1 chips;
means for injecting the probe sequence into a signal path;
means for obtaining a response of the signal path to the probe pseudo-noise sequence;
means for estimating a correlation of the response of the signal path with the reference sequence to obtain a correlation function at a plurality of samples; and
means for estimating a time delay corresponding to a peak of the correlation function, wherein the time delay has an integer chip number portion and a fractional chip number portion.
19. The system of claim 18 , wherein the means for injecting the probe pseudo-noise sequence comprises means for frequency-translating the probe pseudo-noise sequence to a carrier frequency.
20. The system of claim 18 , wherein the means for obtaining a response of the signal path comprises means for frequency-translating the response of the signal path to baseband.
21. The system of claim 18 , wherein the means for estimating the correlation comprises:
means for multiplying the response of the signal path and the reference pseudo-noise sequence to obtain a product;
means for integrating the product to obtain the correlation function.
22. The system of claim 18 , wherein the means for estimating a time delay comprises means for interpolating the correlation function to obtain a fractional chip number portion.
23. A method of reflectometry testing a signal path comprising:
generating a probe sequence of pseudo-random chips at a chip rate R, the probe sequence repeating every L chips;
injecting a test signal into the signal path, the test signal based on the probe sequence;
extracting a response signal from the signal path corresponding to the time domain response of the signal path to the injected test signal;
generating a reference sequence of pseudo-random chips at the chip rate R, the reference sequence repeating every L+1 chips and being equal to the probe sequence over L sequential chips;
correlating the response signal with a signal based on the reference sequence to obtain a plurality of correlation values, a correlation value obtained every L+1 chips; and
estimating a time delay from at least two correlation values, the time delay having resolution of a fraction of the chip time 1/R.
24. The method of claim 23 wherein:
generating a probe sequence of pseudo-random chips comprises clocking a first linear feedback shift register every 1/R references; and
generating a reference sequence of pseudo-random chips comprises clocking a reference linear feedback shift register repeatedly L+1 times, where L clocks are at intervals of 1/R and 1 clock is at an interval of 2/R, and the first linear feedback shift register and reference linear feedback shift register have the same feedback.
25. The method of claim 23 wherein injecting a test signal into the signal path comprises modifying the test signal using a function selected from the group consisting of frequency-shifting, amplifying, attenuating, and filtering.
26. The method of claim 23 wherein extracting a response signal from the signal path comprises modifying the response signal using a function selected from the group consisting of frequency-shifting, amplifying, attenuating, and filtering.
27. The method of claim 23 wherein estimating a time delay comprises estimating a plurality of time delays corresponding to multiple local extrema of the correlation values.
28. The method of claim 23 wherein estimating a time delay comprises interpolating between a local extremum of the correlation values and at least one adjacent correlation value.
29. The method of claim 23 wherein estimating a time delay comprises:
finding a local extremum x m of the correlation values, where m is the integer chip time delay corresponding to the local extremum;
finding the larger x n of the immediately adjacent correlation values x m+1 and x m−1 ;
setting the time delay equal to m+((x n /x m )/(1+x n /x m )) when x m+1 >x m−1 ; and
setting the time delay equal to m−((x n /x m )/(1+x n /x m )) when x m+1 <x m−1 .
30. The method of claim 23 wherein estimating a time delay comprises comparing at least two of the correlation values to a plurality of correlation pattern templates to determine a fractional chip time delay.