Semiconductor memory device and manufacturing method thereof
A semiconductor memory device includes: a memory array; an internal address supplying unit configured to produce a first internal address in response to an external address; a first fuse unit configured to includes fuses and anti-fuses integrated; an address switching circuit configured to produce a second internal address on the basis of the first internal address; and a decoder circuit configured to select a memory cell of the memory array in response to the second internal address. The internal address supplying unit is configured to be capable of fixing a specific address bit in the first internal address. The second internal address includes: fuse independent address bits produced from address bits which is not the specific address bit in the first internal address, independently of a state of the first fuse unit, and a fuse dependent address bit having a value corresponding to the state of the first fuse unit and a vale of the specific address bit.
1. A semiconductor memory device comprising:
a memory array;
an internal address supplying unit configured to produce a first internal address in response to an external address;
a first fuse unit configured to includes fuses and anti-fuses integrated;
an address switching circuit configured to produce a second internal address on the basis of said first internal address; and
a decoder circuit configured to select a memory cell of said memory array in response to said second internal address,
wherein said internal address supplying unit is configured to be capable of fixing a specific address bit in said first internal address,
wherein said second internal address includes:
fuse independent address bits produced from address bits which is not said specific address bit in said first internal address, independently of a state of said first fuse unit, and
a fuse dependent address bit having a value corresponding to said state of said first fuse unit and a value of said specific address bit.
2. The semiconductor memory device according to claim 1 , further comprising:
a second fuse unit configured to includes fuses and anti-fuses integrated,
wherein said internal address supplying unit produces all address bits of said first internal address in response to corresponding respective address bits of said external address, when said second fuse unit is set to a first state, and
said internal address supplying unit produces address bits except for said specific address bit of said first internal address in response to corresponding respective address bits of said external address, and fixes said specific address bit to a predetermined value, when said second fuse unit is set to a second state.
3. The semiconductor memory device according to claim 2 , wherein said memory cell is a flash memory.
4. The semiconductor memory device according to claim 2 , wherein said fuse dependent address bit has one of a value of said specific address bit and a reversed value of said specific address bit.
5. A semiconductor memory device comprising:
a plurality of memory arrays;
an internal address supplying unit configured to produce a first internal address in response to an external address;
a first fuse unit configured to includes fuses and anti-fuses integrated;
an address switching circuit configured to produce a second internal address on the basis of said first internal address; and
a decoder circuit configured to select one of said plurality of memory arrays and a memory cell of said one of the plurality of memory arrays in response to said second internal address,
wherein said internal address supplying unit is configured to be capable of fixing a specific address bit in said first internal address,
wherein said second internal address includes:
fuse independent address bits produced from address bits which is not said specific address bit in said first internal address, independently of a state of said first fuse unit,
a fuse dependent address bit having a value corresponding to said state of said first fuse unit and a value of said specific address bit, and
wherein said decoder circuit selects a part of said plurality of memory arrays in response to said fuse dependent address bit and selects one of said part of said plurality of memory arrays and a memory cell of said one of the part of said plurality of memory arrays in response to said fuse independent address bits.
6. The semiconductor memory device according to claim 5 , further comprising:
a second fuse unit configured to includes fuses and anti-fuses integrated,
wherein said internal address supplying unit produces all address bits of said first internal address in response to corresponding respective address bits of said external address, when said second fuse unit is set to a first state, and
said internal address supplying unit produces address bits except for said specific address bit of said first internal address in response to corresponding respective address bits of said external address, and fixes said specific address bit to a predetermined value, when said second fuse unit is set to a second state.
7. The semiconductor memory device according to claim 6 , wherein said memory cell is a flash memory.
8. The semiconductor memory device according to claim 6 , wherein said fuse dependent address bit has one of a value of said specific address bit and a reversed value of said specific address bit.