Synchronizing a plurality of processors

1. A method of synchronizing a plurality of processors of a system, comprising:

modifying a peripheral component interconnect express (PCIe) protocol to include a completion status encode associated with a synchronization command that indicates whether a condition of the synchronization command is met;

providing a system including:

a memory;

a first processor coupled to the memory;

a second processor; and

an interconnect coupling the second processor to the first processor and the memory; and

employing the modified PCIe protocol on the interconnect.

2. The method of claim 1 further comprising employing the second processor to perform the synchronization command.

3. The method of claim 2 wherein:

the system further includes command processing logic coupled to the memory and the interconnect; and

employing the second processor to perform the synchronization command includes:

issuing the synchronization command on the interconnect;

based on the synchronization command, employing the command processing logic to read data from the memory, modify the read data, and write the modified data to the memory; and

receiving a first completion status encode in the second processor.

4. The method of claim 3 further comprising processing a command subsequent to the synchronization command based on the first completion status encode.

5. The method of claim 3 wherein the data read from the memory by the command processing logic is not transmitted to the second processor.

6. The method of claim 1 wherein the synchronization command is an indivisible combined command to read data from the memory, modify the read data, and write the modified data to the memory such that between the read and write no other processor may access a same memory location with an equivalent indivisible command or may write the same memory location.

7. The method of claim 1 further comprising modifying the PCIe protocol to include a transaction type corresponding to the synchronization command.

8. An apparatus for synchronizing a plurality of processors of a system, comprising:

an interconnect adapted to couple to a first processor and a memory;

a second processor coupled to the interconnect;

wherein the interconnect employs a modified version of a peripheral component interconnect express (PCIe) protocol that includes a completion status encode associated with a synchronization command indicating whether a condition of the synchronization command is met.

9. The apparatus of claim 8 wherein the second processor is adapted to perform the synchronization command.

10. The apparatus of claim 9 further comprising command processing logic coupled to the memory and the interconnect;

wherein the apparatus is adapted to:

issue the synchronization command from the second processor on the interconnect;

based on the synchronization command, employ the command processing logic to read data from the memory, modify the read data, and write the modified data to the memory; and

receive a first completion status encode in the second processor.

11. The apparatus of claim 10 wherein the apparatus is further adapted to process a command subsequent to the synchronization command based on the first completion status encode.

12. The apparatus of claim 10 wherein the data read from the memory by the command processing logic is not transmitted to the second processor.

13. The apparatus of claim 8 wherein the synchronization command is an indivisible combined command to read data from the memory, modify the read data, and write the modified data to the memory such that between the read and write no other processor may access a same memory location with an equivalent indivisible command or may write the same memory location.

14. The apparatus of claim 8 wherein the modified version of the PCIe protocol further includes a transaction type corresponding to the synchronization command.

15. A system for synchronizing a plurality of processors of a system, comprising:

a memory;

a first processor coupled to the memory;

a second processor; and

an interconnect coupling the second processor to the first processor and the memory;

wherein the interconnect employs a modified version of a peripheral component interconnect express (PCIe) protocol that includes a completion status encode associated with a synchronization command indicating whether a condition of the synchronization command is met.

16. The system of claim 15 wherein the second processor is adapted to perform the synchronization command.

17. The system of claim 16 further comprising command processing logic coupled to the memory and the interconnect;

wherein the system is adapted to:

issue the synchronization command from the second processor on the interconnect;

based on the synchronization command, employ the command processing logic to read data from the memory, modify the read data, and write the modified data to the memory; and

receive a first completion status encode in the second processor.

18. The system of claim 17 wherein the system is further adapted to process a command subsequent to the synchronization command based on the first completion status encode.

19. The system of claim 17 wherein the data read from the memory by the command processing logic is not transmitted to the second processor.

20. The system of claim 15 wherein the synchronization command is an indivisible combined command to read data from the memory, modify the read data and write the modified data to the memory such that between the read and write no other processor may access a same memory location with an equivalent indivisible command or may write the same memory location.

21. The system of claim 15 wherein the modified version of the PCIe protocol further includes a transaction type corresponding to the synchronization command.