Non-volatile memory device and method of manufacturing the same
A non-volatile memory device includes isolation layers, a cell trench, a floating gate, a common source region and a word line. The isolation layers define an active region of a substrate. The cell trench is formed in the active region. The cell trench extends in a first direction. The floating gate is formed on the active region and in the cell trench. The common source region is formed on the active region adjacent a second side face of the floating gate and extends in a second direction substantially perpendicular to the first direction. The word line is formed on the active region, which is adjacent to a first side face of the floating gate opposite to the second side face, and the isolation layers and in the cell trench. The word line extends in the second direction.
1. A non-volatile memory device comprising:
a substrate having an active region that is defined by isolation layers;
a cell trench formed at a surface portion of the active region of the substrate, the cell trench extending along a first direction substantially parallel with a lengthwise direction of the isolation layers;
a floating gate formed on the active region to fill in the cell trench;
a word line formed on the active region adjacent a first side face of the floating gate, and the isolation layers to fill up the cell trench, the word line extending along a second direction substantially perpendicular to the first direction; and
a common source region formed in the active region adjacent a second side face of the floating gate that is opposite to the first side face, the common source region extending along the second direction.
2. The non-volatile memory device of claim 1 , wherein the floating gate is partially overlapped with the common source region and the isolation layers.
3. The non-volatile memory device of claim 1 , wherein the floating gate comprises a pair of floating gate patterns spaced apart in the first direction with respect to the common source region.
4. The non-volatile memory device of claim 1 , wherein the active region comprises a first sub-region extending along the first direction and a second sub-region extending along the second direction, and the common source region is formed on the second sub-region.
5. The non-volatile memory device of claim 1 , wherein the common source region is intersected with the cell trench.
6. The non-volatile memory device of claim 1 , further comprising a tunnel oxide layer formed between the active region having the cell trench and the floating gate.
7. The non-volatile memory device of claim 1 , wherein the word line is partially overlapped with the first side face and an upper face of the floating gate, and upper faces of the isolation layers.
8. The non-volatile memory device of claim 1 , further comprising a gate insulation layer for insulating the floating gate from the word line.
9. The non-volatile memory device of claim 1 , further comprising a drain region formed in the active region adjacent the word line.
10. A method of manufacturing a non-volatile memory device, comprising:
forming isolation layers in a substrate to define an active region of the substrate;
forming a cell trench at a surface portion of the active region, the cell trench extending along a first direction substantially parallel with a lengthwise direction of the isolation layers;
forming a floating gate on the active region to fill in the cell trench;
forming a word line on the active region adjacent a first side face of the floating gate and the isolation layers to fill up the cell trench, the word line extending along a second direction substantially perpendicular to the first direction; and
forming a common source region in the active region adjacent a second side face of the floating gate that is opposite to the first side face, the common source region extending along the second direction.
11. The method of claim 10 , wherein forming the cell trench comprises:
forming a mask pattern on the active region to partially expose the active region;
etching the active region using the mask pattern as an etching mask to form the cell trench; and
removing the mask pattern.
12. The method of claim 10 , further comprising forming a tunnel oxide layer on the active region having the cell trench.
13. The method of claim 10 , wherein the floating gate is partially overlapped with the common source region and the isolation layers.
14. The method of claim 10 , wherein forming the common source region comprises doping the active region adjacent to the first side face of the floating gate with impurities.
15. The method of claim 10 , wherein the word line is partially overlapped with the first side face and an upper face of the floating gate, and upper faces of the isolation layers.
16. The method of claim 10 , further comprising forming a gate insulation layer on the floating gate and the active region to insulate the floating gate from the word line.
17. The method of claim 1 , further comprising doping the active region adjacent the word line with impurities to form a drain region, wherein the drain region is formed simultaneously with the common source region.