Low power ROM

1. A read-only memory (ROM) comprising:

a ROM core unit including a plurality of ROM core groups, each ROM core group including a plurality of transistors coupled to a plurality of word lines and a plurality of bit lines;

a word line decoder to select a desired word line from the word lines;

a column decoder to select a desired bit line from the bit lines;

one or more charge units, each charge unit having a plurality of transistors that are coupled to one of a plurality of dummy bit lines, wherein the dummy bit lines are selected by one of the bit lines, the plurality of transistors of each charge unit being deactivated;

a common reference voltage generator coupled to the dummy bit lines to generated a common reference voltage; and

a plurality of sense amplifiers, each coupled to a corresponding ROM core group and the common reference voltage generator,

wherein the common reference voltage generator generates the common reference voltage in response to a voltage charged through the dummy bit lines and transfers the generated common reference voltage to the sense amplifiers.

2. The ROM of claim 1 , wherein gates of the transistors of the charge units are coupled to ground.

3. The ROM of claim 1 , wherein the dummy bit lines includes first, second and third dummy bit lines,

wherein the one or more charge units includes first, second, and third charge units, and

wherein the first, second, and third dummy bit lines are coupled to the first, second and third charge units, respectively.

4. The ROM of claim 3 , wherein the common reference voltage generator comprises:

a first switch unit to precharge the dummy bit lines in response to an inverted precharge signal;

a second switch unit to discharge the dummy bit lines in response to a precharge signal;

a third switch unit to connect the first and second dummy bit lines in response to a first control signal; and

a fourth switch unit to connect the second and third dummy bit lines in response to a second control signal.

5. The ROM of claim 4 , wherein the first switch unit comprises:

first and second PMOS transistors, each being coupled to a power supply voltage and one of the dummy bit lines and is turned on in response to the inverted precharge signal.

6. The ROM of claim 4 wherein the second switch unit comprises an NMOS transistor that is coupled to the ground voltage and the first dummy bit line and is turned on in response to the precharge signal.

7. The ROM of claim 4 , wherein the third switch unit comprises an NMOS transistor that is coupled to the first dummy bit line and the second dummy bit line, and is turned on in response to the first control signal, and

the fourth switch unit comprises an NMOS transistor that is coupled to the second dummy bit line and the third dummy bit line, and is turned on in response to the second control signal.

8. The ROM of claim 4 , wherein the first, second and third charge units are part of the ROM core unit.

9. The ROM of claim 4 , wherein each of the first, second and third charge units has substantially the same configuration as that of the ROM core group.

10. The ROM of claim 4 , wherein the transistors of the first charge unit have gates and sources that are applied with a ground voltage and drains that are coupled to the first dummy bit line, the first charge unit having a capacitor to charge a voltage of the first dummy bit line.

11. The ROM of claim 4 , wherein each of the plurality of sense amplifiers comprises:

first and second NMOS transistors having drains and sources, a drain of each NMOS transistor being coupled to a different bit line, the sources of the first and second NMOS transistors being coupled to a given node, wherein the NMOS transistors are operated according to an output of the column decoder;

a third NMOS transistor that is provided between the given node and the third dummy bit line and operates in response to a control signal; and

a comparator to compare the common reference voltage and a potential of the given node and to generate an output signal.