IP Library Granted Patent US 7,569,909
Granted Patent B2
US 7,569,909 · App. 11/745,980 · Granted Aug 4, 2009

Phase change memory devices and methods for manufacturing the same

Assignees: Industrial Technology Research Institute; Powerchip Semiconductor Corp.; Nanya Technology Corporation; ProMOS Technologies Inc.; Winbond Electronics Corp.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,569,909
App. No.
11/745,980
Granted
Aug 4, 2009
Kind
B2
Abstract

Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the dielectric layer. A first conductive electrode is also embedded in the dielectric layer to penetrate the phase change material layer and extends perpendicular to a top surface of the dielectric layer.

Claims (16)

1. A phase change memory device, comprising:

a substrate;

a dielectric layer formed over the substrate;

a phase change material layer embedded in the dielectric layer; and

a first conductive electrode embedded in the dielectric layer, penetrating the phase change material layer and extending perpendicular to a top surface of the dielectric layer.

2. The phase change memory device as claimed in claim 1 , wherein the phase change material layer surrounds a part of the first conductive electrode along a circumstance of the first conductive electrode.

3. The phase change memory device as claimed in claim 1 , wherein the phase change material layer comprises chalcogenide materials.

4. The phase change memory device as claimed in claim 1 , wherein phase change material layer is disposed in the dielectric layer and extends in the dielectric layer along a direction horizontal to a top surface of the dielectric layer.

5. The phase change memory device as claimed in claim 1 , further comprising a first conductive layer disposed between the substrate and the dielectric layer, wherein the first conductive electrode connects the first conductive layer.

6. The phase change memory device as claimed in claim 5 , further comprising a second conductive layer disposed over the dielectric layer to electrically connect the phase change material layer.

7. The phase change memory device as claimed in claim 6 , further comprising a second conductive electrode disposed in the dielectric layer to electrically connect the phase change material layer and the second conductive layer.

8. The phase change memory device as claimed in claim 1 , further comprising an active device disposed over the substrate and covered by dielectric layer, wherein the first conductive electrode connects the active device.

9. The phase change memory device as claimed in claim 8 , wherein the active device is a transistor and the first conductive electrode connects a source/drain region of the transistor.

10. The phase change memory device as claimed in claim 9 , further comprising a conductive layer disposed over the dielectric layer to electrically connect the phase change material layer.

11. The phase change memory device as claimed in claim 6 , further comprising a second conductive electrode disposed in a second part of the dielectric layer to connect the phase change material layer with the conductive layer.

12. The phase change memory device as claimed in claim 11 , wherein the second conductive electrode penetrates the phase change material layer perpendicular to a top surface of the dielectric layer and the phase change material layer surrounds a part of the second conductive electrode along a circumstance of the second conductive electrode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2010
From: POWERCHIP SEMICONDUCTOR CORP.; NANYA TECHNOLOGY CORPORATION; PROMOS TECHNOLOGIES INC.; WINBOND ELECTRONICS CORP.
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Reel/Frame 024140/0941 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2007
From: HUANG, CHEN-MING
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE; POWERCHIP SEMICONDUCTOR CORP.; NANYA TECHNOLOGY CORPORATON.; PROMOS TECHNOLOGIES INC.; WINBOND ELECTRONICS CORP.
Reel/Frame 019273/0942 →
Priority Claims (1)
TW 96110500 A · Mar 27, 2007 · national
Continuity (1)
Related Publication 20080241741A1 · Oct 2, 2008