IP Library Granted Patent US 7,573,299
Granted Patent B2
US 7,573,299 · App. 11/806,003 · Granted Aug 11, 2009

Semiconductor integrated circuit including output circuit

Assignee: NEC Electronics Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,573,299
App. No.
11/806,003
Granted
Aug 11, 2009
Kind
B2
Abstract

An output circuit includes a differential section configured to amplify an inputted differential signal; a current source section configured to supply a current to the differential section; a load resistance section connected with the differential section; and a control unit configured to set a value of the current from the current source section and a resistance value of the load resistance section based on a signal supplied to the control unit. The output circuit converts the differential signal into an output signal of a different interface level from that of the differential signal and balance-transmits the output signal.

Claims (12)

1. An output circuit, comprising:

a differential section configured to amplify an inputted differential signal;

a current source section configured to supply a current to said differential section;

a load resistance section connected with said differential section; and

a control unit configured to set a value of the current from said current source section and a resistance value of said load resistance section based on a signal,

wherein said output circuit converts said differential signal into an output signal of a different interface level from that of said differential signal and balance-transmits said output signal,

wherein said load resistance section comprises a first resistance section and a second resistance section, and said control unit sets whether or not said first resistance section is to be used and whether or not said second resistance section is to be used,

wherein said second resistance section comprises:

two external resistances connected in series between said two output terminals; and

an external adjustment resistance connected between said power supply and a connection node of said internal resistances.

2. The output circuit according to claim 1 , wherein when a resistance value of each of external resistances is RT, a resistance value of a termination resistance of a receiving circuit is RE, a power supply voltage is VDD, an amplitude of said output signal is VOD, and a common voltage of said output signal is VCM, a resistance value RC of said external adjustment resistance is calculated from the following equation:

RC=RT×RE ×( VDD−VCM−VOD )/{(2 ×RT+RE ) ×VOD}.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Nov 2, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025235/0456 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2007
From: WATARAI, SEIICHI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 019412/0319 →
Priority Claims (1)
JP 2006-150995 · May 31, 2006 · national
Continuity (1)
Related Publication 20070279124A1 · Dec 6, 2007