Low-power multi-output local clock buffer
View Patent ↗An improved circuit for reducing a capacitance load on a processor. The circuit includes a global clock circuit capable of producing a primary timing signal. The circuit further includes a local clock buffer circuit having a plurality of outputs. The local clock buffer circuit is connected to the global clock circuit. The local clock buffer circuit is capable of producing a secondary timing signal based on the primary timing signal. The circuit also includes a latch connected to the local clock buffer circuit. The latch is capable of producing a select signal that controls which outputs of the plurality of outputs are active. Only a third signal, based on the secondary timing signal, controls an operation of the latch.
1. A circuit comprising:
a global clock circuit capable of producing a primary timing signal;
a local clock buffer circuit having a plurality of outputs, wherein the local clock buffer circuit is connected to the global clock circuit, and wherein the local clock buffer circuit is capable of producing a secondary timing signal based on the primary timing signal;
a latch connected to the local clock buffer circuit, wherein the latch is capable of producing a select signal that controls which outputs of the plurality of outputs are active, and wherein only a third signal, based on the secondary timing signal, controls an operation of the latch.
2. The circuit of claim 1 wherein connection between the latch and the global clock is avoided.
3. The circuit of claim 1 wherein the third signal comprises the secondary timing signal.
4. The circuit of claim 1 wherein the third signal comprises an inverse of the secondary timing signal.
5. The circuit of claim 1 wherein the local clock buffer circuit is capable of holding the select signal at a constant value during a first half of a cycle of the local clock buffer circuit, and wherein the local clock buffer circuit is capable of allowing the select signal to change in a second half of the cycle.
6. The circuit of claim 1 wherein the local clock buffer circuit is capable of, responsive to clock activity being gated off due to de-assertion of a clock gate signal, holding the latch open.
7. The circuit of claim 1 wherein the local clock buffer circuit is laid out such that a capacitive load imposed by the latch is buffered by the local clock buffer circuit.
8. The circuit of claim 1 wherein the local clock buffer circuit is laid out such that switching activity of the signal controlling the latch is gated-off when the local clock buffer circuit is gated-off.
9. The circuit of claim 1 further comprising:
a second local clock buffer circuit having a second plurality of outputs, wherein the second local clock buffer circuit is connected to the global clock circuit, and wherein second the local clock buffer circuit is capable of producing a second secondary timing signal based on the primary timing signal;
a second latch connected to the second local clock buffer circuit, wherein the second latch is capable of producing a second select signal that controls which outputs of the second plurality of outputs are active, and wherein only a fourth signal, based on the second secondary timing signal, controls an operation of the second latch.
10. The circuit of claim 9 wherein the local clock buffer circuit is capable of generating the third signal and the fourth signal by combining the secondary timing signal and the second secondary timing signal.
11. The circuit 10 wherein the local clock buffer circuit is capable of combining by inputting the secondary timing signal and the second secondary timing signal into a NOR gate.
12. The circuit of claim 1 wherein the local clock buffer circuit is capable of, responsive to the secondary timing signal being low, avoiding clocking of a capacitance of the local clock buffer circuit.
13. A method for controlling operation of a latch connected to a local clock buffer circuit having a plurality of outputs, the method comprising:
receiving in the local clock buffer circuit a primary timing signal generated by a global clock circuit;
producing, by the local clock buffer circuit, a secondary timing signal based on the primary timing signal;
producing, by the latch, a select signal, wherein the select signal controls which outputs of the plurality of outputs are active; and
controlling operation of the latch using only a third signal, wherein the third signal is based on the secondary timing signal.
14. The method of claim 13 wherein the third signal comprises the secondary timing signal.
15. The method of claim 13 wherein the third signal comprises an inverse of the secondary timing signal.
16. The method of claim 13 further comprising:
holding the select signal at a constant value during a first half of a cycle of the local clock buffer circuit; and
allowing the select signal to change in a second half of the cycle.
17. The method of claim 13 further comprising:
responsive to clock activity being gated off due to de-assertion of a clock gate signal, holding the latch open.
18. The method of claim 13 further comprising:
producing, by a second local clock buffer circuit, a second secondary timing signal based on the primary timing signal;
producing, by a second latch connected to the second local clock buffer, a second select signal, wherein the second select signal controls which outputs of a second plurality of outputs of the second local clock buffer are active; and
controlling operation of the second latch using only a fourth signal, wherein the fourth signal is based on the second secondary timing signal.
19. The method of claim 18 further comprising:
generating the third signal and the fourth signal by combining the secondary timing signal and the second secondary timing signal.
20. The method of claim 13 further comprising:
responsive to the local clock buffer circuit being gated-off, gating off the switching activity of the signal controlling latch.