Semiconductor device having vertical channels and method of manufacturing the same
A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
1. A semiconductor device having vertical channels, the device comprising:
a plurality of active regions protruded from a top surface of the semiconductor substrate;
first element isolation layers which separate adjacent active regions, the first isolation layers extending in a first direction and having top surfaces that are higher than at least the top surfaces of the active regions;
second element isolation layers which extend at a predetermined angle with respect to the first direction, separate the adjacent active regions, and have top surfaces lower than the top surfaces of the active regions so as to expose at least a portion of the sidewalls of the active regions such that vertical channels can be formed;
a gate insulation aver formed on the plurality of active regions; and
gate electrodes formed on the first element isolation layers and the gate insulation layer,
wherein the gate insulation layer and the gate electrodes cover the sidewalls and top surfaces of the exposed portion of the active regions.
2. The semiconductor device of claim 1 further comprising a nitride layer liner formed between the second element isolation layers and the active regions.
3. The semiconductor device of claim 1 , wherein the first and second element isolation layers include silicon oxide layers.
4. The semiconductor device of claim 1 further comprising third element isolation layers that contact both side surfaces of the second element isolation layers, and have top surfaces higher than the top surfaces of the active regions.
5. The semiconductor device of claim 4 , wherein the second element isolation layers and the third element isolation layers are alternately disposed along the direction of the predetermined angle with respect to the first direction.
6. The semiconductor device of claim 1 , wherein the first element isolation layers contact the second element isolation layers.
7. The semiconductor device of claim 1 , wherein the gate electrode extends at a transverse angle with respect to the first direction.
8. The semiconductor device of claim 1 , wherein the semiconductor device is a fin field effect transistor (FET).
9. The semiconductor device of claim 1 , wherein the second element isolation layers extend in a second direction, the second direction not coplanar with the first direction.