Direct memory access controller including first and second transfer setting registers
DMAC includes current transfer setting registers and next transfer setting registers. Each of the current transfer setting registers stores transfer source address, transfer destination address and transfer count. The next transfer setting registers stores a transfer setting of a DMA transfer carried out after completing a DMA transfer according to a current transfer setting stored in the current transfer setting registers as a next transfer setting. Further, flags are provided for controlling to write to each of the next transfer setting registers.
1. A direct memory access (DMA) controller to control a data transfer from a transfer source address to a transfer destination address, the DMA controller comprising:
a first transfer setting register to store a setting value for one of three setting items, the setting items being the transfer source address, the transfer destination address and a transfer count;
a second transfer setting register to store a setting value for the setting item corresponding to the setting value stored in the first transfer setting register, the setting value being transferred to the first transfer setting register; and
a flag to control writing to the second transfer setting register.
2. The DMA controller according to claim 1 , further comprising:
a write detector to detect a writing to the second transfer setting register,
wherein at a detection of a writing to the second transfer setting register by the write detector, the flag is set to a state indicating a write disable.
3. The DMA controller according to claim 1 , wherein the flag can be set to a state indicating the write disable by a CPU.
4. The DMA controller according to claim 1 , wherein the flag is set to a state indicating a write enable at a completion of a DMA transfer according to the setting value stored in the first transfer setting register.
5. The DMA controller according to claim 2 , wherein the flag is set to a state indicating a write enable at a completion of a DMA transfer according to the setting value stored in the first transfer setting register.
6. The DMA controller according to claim 3 , wherein the flag is set to a state indicating a write enable at a completion of a DMA transfer according to the setting value stored in the first transfer setting register.
7. The DMA controller according to claim 1 , wherein the flag is constituted as a part of the second transfer setting register.
8. The DMA controller according to claim 2 , wherein the flag is constituted as a part of the second transfer setting register.
9. The DMA controller according to claim 3 , wherein the flag is constituted as a part of the second transfer setting register.
10. The DMA controller according to claim 4 , wherein the flag is constituted as a part of the second transfer setting register.
11. The DMA controller according to claim 5 , wherein the flag is constituted as a part of the second transfer setting register.
12. The DMA controller according to claim 6 , wherein the flag is constituted as a part of the second transfer setting register.
13. The DMA controller according to claim 1 , further comprising:
a standard transfer count setting register to store a transfer count to be a standard of a comparison; and
a comparator to compare a transfer count decremented along with a progress of a DMA transfer according to a setting value with the transfer count stored in the standard transfer count setting register, the setting value being stored to the first transfer setting register
wherein the comparator generates an interruption at an indication of a match in the comparison.
14. The DMA controller according to claim 2 , further comprising:
a standard transfer count setting register to store a transfer count to be a standard of a comparison; and
a comparator to compare a transfer count decremented along with a progress of a DMA transfer according to a setting value with the transfer count stored in the standard transfer count setting register, the setting value being stored to the first transfer setting register
wherein the comparator generates an interruption at an indication of a match in the comparison.
15. The DMA controller according to claim 3 , further comprising:
a standard transfer count setting register to store a transfer count to be a standard of a comparison; and
a comparator to compare a transfer count decremented along with a progress of a DMA transfer according to a setting value with the transfer count stored in the standard transfer count setting register, the setting value being stored to the first transfer setting register
wherein the comparator generates an interruption at an indication of a match in the comparison.
16. The DMA controller according to claim 4 , further comprising:
a standard transfer count setting register to store a transfer count to be a standard of a comparison; and
a comparator to compare a transfer count decremented along with a progress of a DMA transfer according to a setting value with the transfer count stored in the standard transfer count setting register, the setting value being stored to the first transfer setting register
wherein the comparator generates an interruption at an indication of a match in the comparison.
17. The DMA controller according to claim 5 , further comprising:
a standard transfer count setting register to store a transfer count to be a standard of a comparison; and
a comparator to compare a transfer count decremented along with a progress of a DMA transfer according to a setting value with the transfer count stored in the standard transfer count setting register, the setting value being stored to the first transfer setting register
wherein the comparator generates an interruption at an indication of a match in the comparison.
18. The DMA controller according to claim 6 , further comprising:
a standard transfer count setting register to store a transfer count to be a standard of a comparison; and
a comparator to compare a transfer count decremented along with a progress of a DMA transfer according to a setting value with the transfer count stored in the standard transfer count setting register, the setting value being stored to the first transfer setting register
wherein the comparator generates an interruption at an indication of a match in the comparison.
19. The DMA controller according to claim 7 , further comprising:
a standard transfer count setting register to store a transfer count to be a standard of a comparison; and
a comparator to compare a transfer count decremented along with a progress of a DMA transfer according to a setting value with the transfer count stored in the standard transfer count setting register, the setting value being stored to the first transfer setting register
wherein the comparator generates an interruption at an indication of a match in the comparison.
20. The DMA controller according to claim 8 , further comprising:
a standard transfer count setting register to store a transfer count to be a standard of a comparison; and
a comparator to compare a transfer count decremented along with a progress of a DMA transfer according to a setting value with the transfer count stored in the standard transfer count setting register, the setting value being stored to the first transfer setting register
wherein the comparator generates an interruption at an indication of a match in the comparison.