Power core devices
The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.
1. A device comprising a power core wherein said power core comprises:
at least one embedded singulated capacitor layer containing more than one embedded singulated individual capacitor, each of said embedded singulated individual capacitors comprising a capacitor formed on a metal foil having a thickness of from 1 to 100 microns; and
at least one planar capacitor laminate;
wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said embedded singulated individual capacitors; and
wherein more than one of said embedded singulated individual capacitors in said embedded singulated capacitor layer are connected in parallel to one of the said at least one planar capacitor laminates; and
wherein said power core is interconnected to at least one signal layer.
2. The device of claim 1 wherein said power core comprises multiple embedded singulated capacitor layers and multiple planar capacitor laminates.
3. The device of claim 1 wherein said embedded singulated individual capacitors each comprise at least a first electrode and a second electrode.
4. The device of claim 3 wherein the first electrode and second electrode of the embedded singulated individual capacitors are connected to at least one power terminal of a semiconductor device.
5. The device of claim 4 wherein said semiconductor device is an integrated circuit.
6. The device of claim 4 wherein each of the embedded singulated individual capacitors are placed closer to a power terminal of the semiconductor device than the planar capacitor to which the respective singulated individual capacitor is connected in parallel.
7. The device of claim 1 comprising more than one signal layer wherein said signal layers are connected through conductive vias.
8. The device of claim 1 wherein said device is selected from an interposer, printed wiring board, multichip module, area array package, system-on-package, and system-in-package.
9. The device of claim 1 wherein each of said embedded singulated individual formed on foil capacitors comprises a fired on foil capacitor.
10. The device of claim 1 wherein each of said embedded singulated individual capacitors comprising a capacitor formed on a metal foil having a thickness of from 3 to 75 microns.
11. The device of claim 1 wherein said at least one planar capacitor layer comprises an organic dielectric.
12. The device of claim 1 wherein the organic dielectric of the planar capacitor layer comprises a ceramic-filled organic dielectric.
13. A device comprising a power core for a semiconductor device wherein said power core comprises:
at least one embedded singulated capacitor layer containing more than one embedded singulated individual capacitor, each of said more than one embedded singulated individual capacitors comprising a capacitor formed on a metal foil, said metal foil forming a first electrode of each of said more than one embedded singulated individual capacitors, and each of said more than one embedded singulated capacitors further comprising a second electrode, wherein said first electrode and second electrode of said more than one embedded singulated individual capacitors are connected to at least one power terminal of the semiconductor device;
at least one planar capacitor laminate;
wherein said more than one of said embedded singulated individual capacitors in said embedded singulated capacitor layer are each connected in parallel to one of the said at least one planar capacitor laminate and said planar capacitor laminate serves as a low inductance path to supply a charge to said more than one embedded singulated individual capacitors;
wherein each of said more than one embedded singulated individual capacitors connected in parallel to said planar capacitor are closer to a power terminal of the semiconductor device than is the planar capacitor to which the respective singulated individual capacitor is connected in parallel; and
wherein said power core is interconnected to at least one signal layer.
14. The device of claim 13 wherein said semiconductor device is an integrated circuit.