Phase-change memory device and method of fabricating the same

1. A phase-change memory device comprising:

a semiconductor substrate;

a plurality of bit lines arranged on the semiconductor substrate;

a plurality of word lines arranged on the semiconductor substrate, wherein each word line intersects each bit line; and

a plurality of phase-change material strips positioned between the plurality of bit lines and the plurality of word lines, wherein each phase-change material strip extends along a length of each word line in a direction parallel to each word line and overlaps at least two bit lines.

2. The phase-change memory device of claim 1 , wherein each of the phase-change material strips and each of the word lines have the same width.

3. The phase-change memory device of claim 1 , wherein each of the phase-change material strips is responsive to current to be programmable between at least two resistive states.

4. The phase-change memory device of claim 3 , wherein each of the phase-change material strips includes germanium (Ge), antimony (Sb), and tellurium (Te).

5. The phase-change memory device of claim 3 , further comprising:

an access element between each phase-change material strip and the at least two bit lines overlapped by the phase-change material strip, controlling the current applied to the phase-change material strip.

6. The phase-change memory device of claim 1 , wherein the plurality of word lines are above the plurality of bit lines.

7. The phase-change memory device of claim 1 , wherein the plurality of bit lines are above the plurality of word lines.

8. A phase-change memory device comprising:

a semiconductor substrate;

a plurality of bit lines extending lengthwise on the semiconductor substrate in a first direction;

a plurality of rows of cell diodes respectively located over and electrically connected to the plurality of bit lines, wherein each row of cell diodes extends in the first direction;

a plurality of phase-change material strips extending lengthwise in a second direction over the plurality of rows of cell diodes, wherein each phase-change material strip is electrically connected to cell diodes of at least two rows among the plurality of rows of cell diodes; and

a plurality of word lines respectively located over the plurality of phase-change material strips and extending lengthwise in the second direction,

wherein each phase-change material strip overlaps at least two bit lines.

9. The phase-change memory device of claim 8 , wherein each phase-change material strip and each respective word line have a same width.

10. The phase-change memory device of claim 8 , wherein the plurality of bit lines comprise epitaxial layers of a first conductivity type.

11. The phase-change memory device of claim 10 , wherein each cell diode includes first semiconductor pattern of a first conductivity type and second semiconductor pattern of a second conductivity type overlying the first semiconductor pattern.

12. The phase-change memory device of claim 11 , wherein the first conductivity type is a P-type and the second conductivity type is an N-type.

13. The phase-change memory device of claim 8 , further comprising:

a plurality of bottom electrode contacts on the plurality of cell diodes, electrically connecting the cell diodes with the respective phase-change material strips.

14. The phase-change memory device of claim 8 , further comprising:

a plurality of metal lines on the plurality of word lines, electrically connected to the plurality of bit lines, respectively.

15. The phase-change memory device of claim 14 , wherein the plurality of metal lines extend in the first direction.

16. A method of fabricating a phase-change memory device, the method comprising:

forming a plurality of bit lines extending lengthwise on a semiconductor substrate in a first direction;

forming a plurality of cell diodes in a plurality of rows over the plurality of bit lines, wherein each row of cell diodes extends in the first direction; and

forming a plurality of phase-change material strips and a corresponding plurality of word lines extending lengthwise in a second direction crossing over the plurality of rows,

wherein each phase-change material strip connects with one cell diode of each row of the plurality of rows and overlaps at least two bit lines.

17. The method of claim 16 , wherein each phase-change material strip and each corresponding word line have a same width.

18. The method of claim 16 , wherein the forming of the plurality of bit lines comprises forming bottom mold layer patterns having a plurality of openings on the semiconductor substrate, and forming epitaxial layers of a first conductivity type within the plurality of openings of the bottom mold layer patterns.

19. The method of claim 18 , wherein the forming of the plurality of cell diodes comprises forming top mold layer patterns having a plurality of openings on the bottom mold layer patterns and the bit lines, and forming first semiconductor patterns of a first conductivity type and second semiconductor patterns of a second conductivity type within the plurality of openings of the top mold layer patterns, the second semiconductor patterns overlying the first semiconductor patterns.

20. The method of claim 19 , wherein the first conductivity type is a P-type and the second conductivity type is an N-type.

21. The method of claim 16 , further comprising:

forming a plurality of bottom electrode contacts on the plurality of cell diodes after forming the plurality of cell diodes,

wherein each phase-change material strip electrically connects with the one cell diode of each row of the plurality of rows through a corresponding bottom electrode contact of the plurality of bottom electrode contacts.

22. The method of claim 16 , further comprising:

forming a plurality of metal lines on the plurality of word lines, the plurality of metal lines being electrically connected to the plurality of bit lines, respectively, after forming the phase-change material strips and the word lines.

23. The method of claim 22 , wherein the plurality of metal lines are substantially parallel to the plurality of bit lines, respectively.