Methods of manufacturing semiconductor devices and semiconductor devices manufactured using such a method
A method of manufacturing a semiconductor device includes forming a pillar-shaped active region by etching a portion of a semiconductor substrate, forming a blocking film selectively exposing a sidewall of a lower portion of the pillar-shaped active region, and forming a bit-line selectively on the exposed sidewall of the lower portion of the pillar-shaped active region.
1. A semiconductor device, comprising:
a semiconductor substrate including pillar-shaped active regions thereon;
a plurality of transistors each having a source region at an upper end of the respective pillar-shaped active region, a drain region in the respective pillar-shaped active region so as to be spaced from the source region, and a gate electrode formed on a gate insulating film on a sidewall of the upper end of the respective pillar-shaped active region between the source region and the drain region; and
bit-lines on sidewalls of lower ends of the pillar-shaped active regions, the bit lines being respectively connected with the respective drain region and spaced from the respective gate electrode, the sidewalls of the lower ends of the pillar-shaped active regions being curved and/or rounded,
wherein the bit lines have a curved and/or rounded cross-sectional shape.
2. The semiconductor device as claimed in claim 1 , wherein the lower end of the pillar-shaped active region includes an upper portion and a lower portion, wherein the drain region is formed in the upper portion of the lower end of the pillar-shaped active region and the sidewall where the respective bit-line is formed is in the lower portion of the lower end of the pillar-shaped active region.
3. The semiconductor device as claimed in claim 2 , wherein the upper portion of the lower end of the pillar-shaped active region is wider than the lower portion of the lower end of the pillar-shaped active region.
4. The semiconductor device as claimed in claim 1 , wherein the sidewall of the upper end of the pillar-shaped active region on which the gate insulating layer and the gate electrode are formed includes a recessed portion.
5. The semiconductor device as claimed in claim 1 , wherein the gate electrode includes at least one of TiN, TaN, WN and WCN.
6. The semiconductor device as claimed in claim 5 , wherein the gate electrode is connected with a word-line including a metal.
7. The semiconductor device as claimed in claim 1 , wherein the bit-line is a silicide film.
8. The semiconductor device as claimed in claim 7 , wherein the silicide film is a metallic silicide film including at least one of Co, Ni, Mo, Ta, Zr, W, and Ti.
9. A semiconductor device, comprising:
a semiconductor substrate including a pillar-shaped active region thereon;
a transistor including a source region at an upper end of the pillar-shaped active region, a drain region in the pillar-shaped active region that is spaced from the source region, and a gate electrode on a gate insulating film on a sidewall of the upper end of the pillar-shaped active region between the source region and the drain region; and
a bit-line on a sidewall of a lower end of the pillar-shaped active region, the bit line being connected with the drain region and spaced from the gate electrode, wherein:
the lower end of the pillar-shaped active region includes an upper portion and a lower portion,
the drain region is in the upper portion of the lower end of the pillar-shaped active region,
the sidewall corresponding to the bit-line is in the lower portion of the lower end of the pillar-shaped active region, and
the upper portion of the lower end of the pillar-shaped active region is wider than the lower portion of the lower end of the pillar-shaped active region.