Memory module with stacked semiconductor devices
Embodiments are described in which a stacked arrangement of integrated circuit packages comprises a dummy substrate comprising an embedded discrete or distributed capacitor connected to first and/or second power voltages, or an embedded termination register connected to one or more clock, control, address, and/or data signals(s).
1. A semiconductor device, comprising:
a stacked arrangement of integrated circuit packages, each package comprising;
a substrate and at least one integrated circuit chip, the substrate including a first power terminal to receive a first power signal and a second power terminal to receive a second power signal and,
a dummy substrate without an integrated circuit chip formed on the stacked arrangement of integrated circuit packages and comprising a third power terminal to receive the first power signal, a fourth power terminal to the second power signal, and an embedded discrete capacitor embedded in the dummy substrate and connected between the third power terminal and the fourth power terminal.
2. The semiconductor device of claim 1 , wherein each package further comprises:
a first via and a second via respectively communicating the first power signal and second power signal through the substrate,
wherein the first via and the second via are connected to the third power terminal and the fourth power terminal, respectively.
3. The semiconductor device of claim 2 , wherein the first, second, third and fourth power terminals have a ball land structure.
4. The semiconductor device of claim 3 , wherein an anode of the embedded discrete capacitor is formed directly on the first power terminal ball land structure and a cathode of the embedded discrete capacitor is formed directly on the second power terminal ball land structure.
5. The semiconductor device of claim 3 , wherein one of an anode and a cathode of the embedded discrete capacitor are respectively connected to the first power terminal ball land structure and second power terminal ball land structure via an electrical pattern.
6. The semiconductor device of claim 3 , wherein the dummy substrate further comprises an insulating layer embedding the discrete capacitor, the insulating layer comprising:
a first principal surface facing the stacked arrangement of integrated circuit packages and comprising the first power terminal ball land structure and the second power terminal ball land structure;
a second principal surface opposite the first principal surface; and,
a protective layer formed on the second principal surface.
7. The semiconductor device of claim 1 , wherein the memory device package comprises one of a chip scale package (CSP), ball grid array (BGA) package, board-on-chip (BOC) package, or a through-hole stack package.
8. The semiconductor device of claim 1 , wherein the first power signal is Vcc and the second power signal is Vss.
9. The semiconductor device of claim 1 , wherein the dummy substrate further comprises:
an insulating layer embedding the discrete capacitor and comprising a first principal surface facing the stacked arrangement of integrated circuit packages and a second principal surface opposite the first principal surface;
a conductive electrode sheet formed on the second principal surface;
a via electrically connecting the conductive electrode sheet through the insulating layer to one of the first power terminal or the second power terminal; and,
a protective layer formed on the conductive electrode sheet.
10. The semiconductor device of claim 9 , wherein the dummy substrate further comprises:
a first power terminal ball land structure formed on the first principal surface and electrically connected to an anode of the embedded discrete capacitor; and,
a second power terminal ball land structure formed on the first principal surface and electrically connected to a cathode of the embedded discrete capacitor.
11. The semiconductor device of 9 , wherein the conductive electrode sheet comprises one or more voids adapted to thermally stabilize the conductive electrode sheet.
12. A semiconductor device, comprising:
a stacked arrangement of integrated circuit (IC) packages, each package comprising;
a substrate and at least one integrated circuit chip, the substrate receiving a first power signal and a second power signal; and,
a dummy substrate without an integrated circuit chip formed on the integrated circuit package at a top position within the stacked arrangement of IC packages and comprising:
an insulating layer comprising a first principal surface facing the integrated circuit package and a second principal surface opposite the first principal surface;
a first conductive electrode sheet formed on the first principal surface and electrically connected to a first one of the first power signal or the second power signal;
a second conductive electrode sheet formed on the second principal surface;
a via electrically connecting the second conductive electrode sheet through the insulating layer to a second one of the first power signal or the second power signal.
13. The semiconductor device of claim 12 , further comprising:
a protective layer formed on at least one of the first or second conductive electrode sheets.
14. The semiconductor device of claim 12 , wherein the insulating layer comprises a dielectric material.
15. A semiconductor device, comprising:
a stacked arrangement of integrated circuit packages, each package comprising;
a substrate and at least one integrated circuit chip, the substrate receiving a first power signal and a second power signal; and,
a dummy substrate without an integrated circuit chip formed on the stacked arrangement of integrated circuit packages and comprising an embedded termination register embedded in the dummy substrate and electrically connected to the at least one signal line communicating at least one signal.
16. The semiconductor device of claim 15 , wherein the embedded termination register is formed from a discrete resistive element, resistive paste, or a sheet resistor.
17. The semiconductor device of claim 15 , wherein the at least one signal line comprises a plurality of signal lines communicating a differential signal.
18. The semiconductor device of claim 15 , wherein the at least one signal comprises a plurality of control signals, address signals, or data signals; and
wherein the at least one signal line comprises signal line bus transmitting the plurality of control signals, address signals, or data signals.
19. The semiconductor device of claim 15 , further comprising:
a protective layer formed on an upper surface of the dummy substrate.
20. The semiconductor device of claim 15 , wherein the dummy substrate further comprises an embedded discrete capacitor connected between the first and second power signals.