Display with system-on-panel design
A display adopting system-on-panel (SOP) design comprising a pixel array, a driving unit, a timing controller, and a first synchronization unit is provided. The pixel array is electrically connected with the driving unit. The timing controller generates a first set of timing signals to the driving unit. The first synchronization unit is set adjacent to an input of the driving unit for synchronizing the first set of timing signals.
1. A display panel, comprising:
a pixel array;
a source driver electrically connected to the pixel array;
a scan driver electrically connected to the pixel array;
a timing controller configured to apply a first set of timing signals to the source driver and a second set of timing signals to the scan driver;
a first synchronization unit, electrically connected to an input of the source driver for synchronizing the first set of timing signals;
a second synchronization unit, electrically connected to an input of the scan driver for synchronizing the second set of timing signals; and
a fourth synchronization unit, electrically connected to another input of the source driver, for synchronizing display data applied to the source driver through the fourth synchronization unit with the first set of timing signals.
2. The display panel according to claim 1 , wherein the second set of timing signals includes a second clock signal and a second starting signal, and the second synchronization unit synchronizes the second clock signal with the second starting signal.
3. The display panel according to claim 1 , wherein the second synchronization unit includes a second synchronization clock.
4. The display panel according to claim 1 , wherein the timing controller further applies a synchronizing signal to the first synchronization unit and the second synchronization unit to synchronize the first set of timing signals with the second set of timing signals.
5. The display panel according to claim 1 , wherein the timing controller further applies a synchronizing signal to the first synchronization unit and the fourth synchronization unit to synchronize the first set of timing signals with the display data.
6. The display panel according to claim 1 , wherein the fourth synchronization unit includes a fourth synchronization clock for synchronizing the first set of timing signals with the display data.
7. The display panel according to claim 1 , wherein the first synchronization unit is configured to synchronize the first set of timing signals with display data applied to the source driver through the first synchronization unit.
8. The display panel according to claim 1 , wherein the first set of timing signals includes a first clock signal and a first starting signal, and the first synchronization unit synchronizes the first clock signal with the first starting signal.
9. The display panel according to claim 1 , wherein the first synchronization unit includes a first synchronization clock.