IP Library Granted Patent US 7,617,387
Granted Patent B2
US 7,617,387 · App. 11/535,536 · Granted Nov 10, 2009

Methods and system for resolving simultaneous predicted branch instructions

Assignee: QUALCOMM Incorporated
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Quick Facts
Patent No.
US 7,617,387
App. No.
11/535,536
Granted
Nov 10, 2009
Kind
B2
Abstract

A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.

Claims (37)

1. A method comprising:

processing two or more predicted branch instructions, each predicted branch instruction having a predicted state and a corrected state, the predicted branch instructions entering a resolution stage;

selecting one of the corrected states from one of the predicted branch instructions;

determining that at least one of the predicted branch instructions has mispredicted;

performing a first flush of a first portion of an instruction pipeline;

initiating instruction fetches based on the selected corrected state;

after performing the first flush and after initiating instruction fetches based on the selected corrected state, determining whether an oldest predicted branch instruction that has mispredicted has the selected corrected state;

when the oldest predicted branch instruction that has mispredicted has the selected corrected state, performing a first flush of a second portion of the instruction pipeline, wherein the second portion differs from the first portion; and

when the oldest predicted branch instruction that has mispredicted does not have the selected corrected state:

performing a second flush of the first portion of the instruction pipeline;

initiating second instruction fetches based on the selected corrected state of the oldest predicted branch instruction that has mispredicted; and

performing a second flush of the second portion of the instruction pipeline.

2. The method of claim 1 wherein the predicted stale further comprises a target address.

3. The method of claim 1 wherein the selected corrected slate corresponds to the oldest one of the predicted branch instructions.

4. The method of claim 1 wherein the selected corrected state is randomly chosen.

5. The method of claim 1 wherein the selected corrected state is based on which pipeline last predicted.

6. The method of claim 1 wherein the selected corrected state is based on which pipeline last mispredicted.

7. The method of claim 1 wherein the selected corrected state is based on a type of the predicted branch instruction.

8. A method of resolving predicted branch instructions prior to validation of the predicted branch instructions in a plurality of pipelines, the method comprising:

processing two or more predicted branch instructions, each predicted branch instruction having a predicted state and a corrected state, said predicted branch instructions entering a resolution stage in separate pipelines;

selecting one of the corrected states from one of said predicted branch instructions prior to determining that at least one of the predicted branch instructions has mispredicted;

performing a first flush of a first portion of an instruction pipeline;

directing instruction fetches based on the selected corrected state;

after performing the first flush and after directing instruction fetches based on the selected corrected state, determining whether an oldest predicted branch instruction that has mispredicted has the selected corrected state;

when the oldest predicted branch instruction that has mispredicted has the selected corrected state, performing a first flush of a second portion of the instruction pipeline, wherein the second portion differs from the first portion; and

when the oldest predicted branch instruction that has mispredicted does not have the selected corrected state;

performing a second flush of the first portion of the instruction pipeline;

directing second instruction fetches based on the selected corrected state of the oldest predicted branch instruction that has mispredicted; and

performing a second flush of the second portion of the instruction pipeline.

9. The method of claim 8 wherein the predicted state of at least one of the predicted branch instructions further comprises a branch direction.

10. The method of claim 8 wherein the predicted suite of at least one of the predicted branch instructions further comprises a predicted mode of a processor.

11. The method of claim 10 wherein the processor is configured to execute instructions having a first instruction length in a first mode and to execute instructions having a second instruction length in a second mode, wherein the second instruction length is shorter than the first instruction length, and wherein the predicted mode is one of the first mode or the second mode.

12. The method of claim 8 wherein the selected corrected state corresponds to the oldest one of the predicted branch instructions.

13. The method of claim 8 wherein the selected corrected state is randomly chosen.

14. The method of claim 8 wherein the selected corrected state is selected based on which pipeline last predicted.

15. The method of claim 8 wherein the selected corrected state is selected based on which pipeline last mispredicted.

16. The method of claim 8 wherein the selected corrected state is selected based on a type of the predicted branch instruction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2006
From: SMITH, RODNEY WAYNE; STEMPEL, BRIAN MICHAEL; DIEFFENDERFER, JAMES NORRIS; SARTORIUS, THOMAS ANDREW
To: QUALCOMM INCORPORATED
Reel/Frame 018309/0969 →
Continuity (1)
Related Publication 20080077781A1 · Mar 27, 2008