Cache memory and method of controlling memory
A cacheable memory access space receives memory access addresses having different data structures according to a status of a cache capacity from a processor. A cache hit detector determines whether data has been hit based on a mode signal, an enbblk [n] signal, and a signal indicating whether the way is valid or invalid, which are preset in the cache hit detector, a tag comparison address received from the cacheable memory access space, and a tag received from the storage unit.
1. A cache memory that employs a set associative method including a plurality of ways and lines, and passes data to a processor according to a request from the processor, the cache memory comprising:
a holding unit that holds the ways divided into a plurality of blocks in each of the ways, each of the blocks including a plurality of tag information, wherein a first entry address of the tag information is formed as the entry address when an entire cache capacity of a way is used, and a second entry address of the tag information is formed as the entry address using a different bit from the first entry address without changing a region of the entry address that is used when one block of the way is disabled, the tag information including the entry address and a status bit, the entry address being compared with a tag comparison address that determines whether the data specified by the line address is valid, and the status bit unit including information indicating whether the tag information is valid;
an access-address acquiring unit that acquires an access address that includes a line address of a position of the data requested by the processor and the tag comparison address;
a cache hit detector that determines which one block of the way is exclusively enabled; and
a determination processing unit that determines whether the data requested by the processor has been hit, based on statuses of the access address and a result of a determination by the cache hit detector.
2. The cache memory according to claim 1 , wherein
the line address includes specification information that specifies a block included in the way, and
a single block from among the blocks included in the way is specified by the specification information.
3. The cache memory according to claim 1 , wherein the determination processing unit specifies beforehand a way and a block to be used, according to a status of use of a cache capacity.
4. The cache memory according to claim 1 , wherein an address configuration of the tag comparison address is changed according to a status of use of a cache capacity.
5. A method of controlling a memory that is applied to a cache memory that employs a set associative method including a plurality of ways and a plurality of lines, a plurality of blocks including a plurality of lines in each of the ways, and passes data to a processor according to a request from the processor, the method comprising:
holding the ways, that are divided into a plurality of blocks in each of the ways, in a holding unit, each of the blocks including a plurality of tag information, and a first entry address of the tag information is formed as the entry address when an entire cache capacity of a way is used, and a second entry address of the tag information is formed as the entry address using a different bit from the first entry address without changing a region of the entry address that is used when one block of the way is disabled, the tag information including the entry address and a status bit, the entry address being compared with a tag comparison address that determines whether the data specified by the line address is valid, and the status bit including information indicating whether the tag information is valid;
acquiring an access address that includes a line address of a position of the data requested by the processor, and the tag comparison address;
determining which one block of the way is -exclusively enabled without reducing the number of ways;
determining whether the data requested by the processor has been hit, based on statuses of the access address and a result of a determination of which one block of the way is exclusively -enabled;
searching the data requested by the processor from the cache memory when the data requested by the processor has been hit; and
passing the data searched to the processor.