Integrated circuit incorporating decoupling capacitor under power and ground lines
View Patent ↗A semiconductor device is composed of: an array of CMOS primitive cells provided in a circuit region; a power supply line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a ground line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a first decoupling capacitor provided under the power supply line; a second decoupling capacitor provided under the ground line. The first decoupling capacitor is formed of a PMOS transistor having a gate connected to the ground line. At least one of the source and drain of the PMOS transistor is connected to the power supply line. The second decoupling capacitor is formed of an NMOS transistor having a gate connected to the power supply line. At least one of the source and drain of the NMOS transistor is connected to the ground line.
1. The semiconductor device comprising:
an array of CMOS primitive cells provided in a circuit region;
a first power supply line extended along said array of said CMOS primitive cells and connected to the CMOS primitive cells;
a first ground line extended along said array of said CMOS primitive cells and connected to the CMOS primitive cells;
a first decoupling capacitor provided under said power supply line;
a second decoupling capacitor provided under said ground line,
wherein said first decoupling capacitor is formed of a first PMOS transistor having a gate connected to said first ground line, at least one of a source and drain of said first PMOS transistor being connected to said first power supply line, and
wherein said second decoupling capacitor is formed of a first NMOS transistor having a gate connected to said first power supply line, at least one of a source and drain of said first NMOS transistor being connected to said first ground line:
a second power supply line extended along said first power supply line and fixing an electrical potential of an N-well;
a second ground line extended along said first ground line and fixing an electrical potential of a P-well: and
an N-type diffusion layer provided under said second power supply line, and connecting said N-well to said second power supply line; and
a P-type diffusion layer provided under said second ground line, and connecting said P-well to said second ground line, and
wherein said N-type diffusion layer is positioned between said first decoupling capacitor and said array of said CMOS primitive cells, and said P-type diffusion layer is positioned between said second decoupling capacitor and said array of said CMOS primitive cells.