IP Library › Granted Patent US 7,642,113
Granted Patent B2
US 7,642,113 · App. 11/594,196 · Granted Jan 5, 2010

Semiconductor wafer dividing method

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,642,113
App. No.
11/594,196
Granted
Jan 5, 2010
Kind
B2
Abstract

An element is formed on the major surface of a semiconductor wafer, and a groove is formed in the back surface of the semiconductor wafer along a dicing line or chip dividing line by a mechanical or chemical method. A modified layer is formed by irradiating the groove with a laser, and the semiconductor wafer is divided by using the modified layer as a starting point. The back surface of the semiconductor wafer is removed to at least the depth of the groove.

Claims (35)

1. A semiconductor device fabrication method comprising:

forming an element on a major surface of a semiconductor wafer;

forming a groove in a back surface of the semiconductor wafer along one of a dicing line and a chip dividing line by one of a mechanical method and a chemical method;

forming a modified layer in a position of the semiconductor wafer deeper than the groove by irradiating the groove with a laser;

dividing the semiconductor wafer by using the modified layer as a starting point; and

removing the back surface of the semiconductor wafer to at least a depth of the groove.

2. A method according to claim 1 , wherein the mechanical method forms a groove in the back surface of the semiconductor wafer by using a dicing blade.

3. A method according to claim 1 , wherein the chemical method forms a groove in the back surface of the semiconductor wafer by etching.

4. A method according to claim 1 , wherein dividing the semiconductor wafer cleaves the semiconductor wafer by breaking.

5. A method according to claim 1 , wherein dividing the semiconductor wafer separates the modified layer by expanding a tape adhering to the semiconductor wafer.

6. A semiconductor device fabrication method comprising:

forming an element on a major surface of a semiconductor wafer;

forming a groove with a first depth in a back surface of the semiconductor wafer along one of a dicing line and a chip dividing line;

forming a modified layer with a second depth smaller than the first depth in a position of the semiconductor wafer deeper than the groove by irradiating the groove with a laser;

dividing the semiconductor wafer by cleavage by using the modified layer as a starting point; and

forming a semiconductor chip whose sidewall is a cleavage plane by removing the back surface of the semiconductor wafer to a sum of the first depth and the second depth.

7. A method according to claim 6 , wherein forming the groove forms a groove in the back surface of the semiconductor wafer by using a dicing blade.

8. A method according to claim 6 , wherein forming the groove forms a groove in the back surface of the semiconductor wafer by etching.

9. A method according to claim 6 , wherein forming the modified layer modifies the semiconductor wafer in the groove by scanning the laser which irradiates the groove once.

10. A method according to claim 6 , wherein dividing the semiconductor wafer by cleavage cleaves the semiconductor wafer by breaking.

11. A method according to claim 6 , further comprising affixing a surface protective tape to the major surface of the semiconductor wafer after forming the element, and extending a space between semiconductor chips by expanding the surface protective tape after dividing the semiconductor wafer by cleavage.

12. A method according to claim 6 , wherein the first depth of the groove is larger than a sum of a thickness of the formed semiconductor chip, a margin of grinding, and the second depth.

13. A method according to claim 6 , wherein the first depth of the groove exceeds 60% of a thickness of the semiconductor wafer.

14. A semiconductor device fabrication method comprising:

forming an element on a major surface of a semiconductor wafer;

forming a groove with a first depth in a back surface of the semiconductor wafer along one of a dicing line and a chip dividing line, the groove being formed such that a second depth of one scan which is modifiable by laser irradiation remains in the back surface of the semiconductor wafer;

forming a modified layer reaching the major surface of the semiconductor wafer by irradiating the groove with a laser;

dividing the semiconductor wafer by using the modified layer as a starting point; and

forming a semiconductor chip whose sidewall is the modified layer by removing the back surface of the semiconductor wafer to at least the first depth.

15. A method according to claim 14 , wherein the first depth of the groove is larger than a sum of a thickness of the formed semiconductor chip and a margin of grinding.

16. A method according to claim 14 , wherein forming the groove forms a groove in the back surface of the semiconductor wafer by using a dicing blade.

17. A method according to claim 14 , wherein forming the groove forms a groove in the back surface of the semiconductor wafer by etching.

18. A method according to claim 14 , wherein forming the modified layer forms a modified layer by scanning the laser which irradiates the groove once.

19. A method according to claim 14 , which further comprises affixing a surface protective tape to the major surface of the semiconductor wafer after forming the element, and

in which dividing the semiconductor wafer separates the semiconductor wafer by using the modified layer as a starting point by expanding the surface protective tape.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2006
From: KUROSAWA, TETSUYA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 018709/0518 →
Priority Claims (1)
JP 2005-325022 · Nov 9, 2005 · national
Continuity (1)
Related Publication 20070105345A1 · May 10, 2007