Branch target aware instruction prefetching technique

1. A processor comprising:

a fetch unit wherein said fetch unit, in sequence, fetches an instruction fetch group including at least one branch instruction and then prefetches an instruction prefetch group irrespective of a location of a branch target of said at least one branch;

an instruction store for storing said instruction fetch group including at least one branch instruction and said instruction prefetch group wherein said instruction prefetch group sequentially follows said instruction fetch group; and

logic to characterize a branch target of said at least one branch instruction with respect to fetch group boundaries of said instruction fetch group and said instruction prefetch group, and the processor tailoring instruction prefetching based, at least in part, on the characterizations of the branch target.

2. The processor of claim 1 , wherein the logic characterizes the branch target based, at least in part, on whether the branch target resides within or beyond a fetch group boundary.

3. The processor of claim 2 , wherein the fetch group boundary delimits a memory region that is contiguous with a currently fetched memory region.

4. The processor of claim 3 , wherein the logic further characterizes branch targets based, at least in part, on whether the branch targets reside within the currently fetched memory region.

5. The processor of claim 1 , wherein the logic characterizes branch targets at least with offsets indicated by branch instructions.

6. The processor of claim 1 , wherein the instruction store hosts predecode information for the instructions, the predecode information characterizing branch target locations.

7. A processor comprising:

an instruction store unit operable to store an instruction fetch group including at least one branch instruction and an instruction prefetch group wherein said instruction prefetch group sequentially follows said instruction fetch group;

logic coupled with the instruction store unit, the logic operable to characterize a branch target, based upon prediction information associated with said at least one branch instruction, with respect to a fetch boundary and to regulate instruction prefetching based, at least in part, on the characterization of branch targets wherein when said prediction information includes one of not-taken, and weakly taken, the instruction prefetch group is prefetched even when the characterization of the branch target is beyond the instruction prefetch group; and

a fetch unit coupled with the instruction store unit, the fetch unit operable, in sequence (i) to fetch instructions from the instruction store unit and then (ii) to prefetch instructions from the instruction store unit based on said characterization based upon said prediction information.

8. The processor of claim 7 , wherein the logic comprises:

a shifter operable to shift instruction addresses; and

a compare unit operable to compare shifted addresses of instructions and shifted address of branch targets.

9. The processor of claim 7 , wherein the logic includes an adder operable to add the offset of branch type instructions to the branch type instruction address.

10. The processor of claim 7 further comprising a set of one or more fetch buffers operable to host fetched instructions.

11. An apparatus comprising:

a branch characterization unit operable to characterize branch instructions based on prediction information associated with said branch instructions wherein said prediction information includes one of taken, not-taken, and weakly taken;

an instruction store unit coupled with the branch characterization unit, the instruction store unit operable to host instructions and their predecode information, wherein the predecode information indicates branch targets with respect to a fetch boundary; and

a fetch unit to prefetch groups of instructions from the instruction store unit in accordance with their predecode information wherein when said prediction information includes one of not-taken, and weakly taken, a branch instruction is characterized for pre fetching even when a branch target of the branch instruction is beyond a next instruction fetch group.

12. The apparatus of claim 11 , wherein the branch characterization unit is operable to generate predecode information that characterizes branch instructions.

13. The apparatus of claim 11 , wherein the instruction store unit includes the branch characterization unit.

14. The apparatus of claim 11 further comprising an instruction scheduling unit operable to examine instructions and generate their predecode information.

15. The apparatus of claim 11 further comprising a decode unit.

16. A computer-processor based method comprising:

fetching an instruction fetch group;

prefetching, in sequence following said fetching, an instruction prefetch group wherein said instruction prefetch group sequentially follows said instruction fetch group;

analyzing branch instructions in said instruction fetch group to determine branch target boundaries for instructions in said instruction fetch group; and

analyzing branch prediction information for any of said branch instructions having a branch target boundary outside a boundary of said instruction fetch group and a boundary of said instruction prefetch instruction group to determine whether to continue sequential prefetching wherein when said branch prediction information includes one of not-taken, and weakly taken for a branch instruction, sequential prefetching continues even when a branch target for that branch instruction is beyond an instruction prefetch group.