IP Library › Granted Patent US 7,652,379
Granted Patent B2
US 7,652,379 · App. 11/895,779 · Granted Jan 26, 2010

Bond pad stacks for ESD under pad and active under pad bonding

Assignee: National Semiconductor Corporation
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Quick Facts
Patent No.
US 7,652,379
App. No.
11/895,779
Granted
Jan 26, 2010
Kind
B2
Abstract

A combination of layout improvements and inner layer dielectric (ILD) material improvements provides a bond pad stack that is robust for both gold (Au) and copper (Cu) wires in circuits with only one or two pad metal layers. The layout improvements involve removing all vias between the top metal layer and the metal layers below top metal in the area under the passivation opening (where probe tips and the bond wire are placed). This allows for a more homogenous material without via discontinuities, thereby reducing stress concentration points in the ILD. The ILD material improvement involves adding a layer of silicon nitride in addition to the silicon oxide layer. Traditionally, the ILD consists of either spun-on or high density plasma (HDP) oxides. The growth of the thin layer of silicon nitride over the oxide on the topmost ILD layer provides a composite of significantly increased toughness and prevents cracks or other damage from propagating into the underlying active circuits and routing.

Claims (18)

1. A bond pad structure for an integrated circuit, the structure comprising:

one or more lower conductive layers having dielectric material formed therebetween, each lower conductive layer having a width that is less than or equal to a first width;

a top conductive layer formed over the one or more lower conductive layers and having dielectric material formed between the top conductive layer and the one or more lower conductive layers, the top conductive layer having a second width that is greater than the first width such that the top conductive layer includes a first portion that is formed over the one or more lower conductive layers and a second portion that extends beyond the first width of the one or more lower conductive layers;

a first passivation layer formed on the top conductive layer and having an opening formed therethrough to expose an upper surface area of the second portion of the top conductive layer;

a conductive bond pad layer formed on the first passivation layer such that the conductive bond pad layer includes a first portion that is formed over the first portion of the top conductive layer and a second portion that extends through the opening in the first passivation layer and into electrical contact with the exposed upper surface area of the second portion of the top conductive layer; and

a second passivation layer that is formed on the conductive bond pad layer and having an opening formed therethrough to expose a bond pad surface area of the first portion of the conductive bond pad layer such that the exposed bond pad surface area is formed over the one or more lower conductive layers.

2. The bond pad structure of claim 1 , wherein the dielectric material comprises silicon oxide.

3. The bond pad structure of claim 1 , wherein the dielectric material comprises deposited silicon oxide.

4. The bondpad structure of claim 1 , wherein the first passivation layer comprises silicon nitride.

5. The bond pad structure of claim 1 , wherein the bond pad layer comprises aluminum.

6. The bond pad layer of claim 1 , wherein the second passivation layer comprises silicon nitride.

7. The bond pad layer of claim 1 , wherein the second passivation layer comprises a benzocyclobutene (BCB)-based polymer dielectric.

8. A method of forming a bond pad stack structure, the method comprising:

forming one or more lower conductive layers having dielectric material formed therebetween, each lower conductive layer having a width that is less than or equal to a first width;

forming a top conductive layer over the one or more lower conductive layers such that the top conductive layer and the lower conductive layers have dielectric material formed therebetween, the top conductive layer having a second width that is greater than the first width such that the top conductive layer comprises a first portion that is formed over the one or more lower conductive layers and a second portion that extends beyond the first width of the one or more lower conductive layers;

forming a first passivation layer over the top conductive layer such that the first passivation layer has an opening formed therethrough to expose an upper surface area of the second portion of the top conductive layer;

forming a conductive bond pad layer over the first passivation layer such that the conductive bond pad layer includes a first portion formed over the first portion of the top conductive layer and a second portion that extends through the opening in the first passivation layer and into electrical contact with the top conductive layer; and

forming a second passivation layer over the conductive bond pad layer and having an opening formed therethrough to expose a bond pad surface area of the first portion of the conductive bond pad layer such that the bond pad surface area is formed over the one or more lower conductive areas.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2007
From: PODDAR, ANINDYA
To: NATIONAL SEMICONDUCTOR CORPORATION
Reel/Frame 020136/0351 →
Continuity (2)
Provisional Application 6096160900 · Jul 23, 2007
Related Publication 20090026621A1 · Jan 29, 2009