Power-off apparatus, systems, and methods
Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.
1. An apparatus comprising: a first voltage generator to generate a bias voltage; a memory cell comprising a transistor and a capacitor, the capacitor coupled between the transistor and plate voltage, the capacitor having a storage node associated with a storage node voltage, the first voltage generator generating the bias voltage such that the bias voltage rises from a voltage less than a reference voltage to a voltage less than the storage node voltage, and the bias voltage is maintained at less than or equal to the storage node voltage, at least partially in response to the apparatus entering into a power off mode, wherein the first voltage generator comprises a circuit to control a rate at which the bias voltage rises to the reference voltage, and the bias voltage reaches the reference voltage after a time delay.
2. The apparatus of claim 1 , wherein the reference voltage is approximately zero volts.
3. The apparatus of claim 1 , comprising a second voltage generator to generate the plate voltage.
4. The apparatus of claim 1 , wherein the bias voltage rises to approximately the reference voltage.
5. The apparatus of claim 1 , comprising a second voltage generator to adjust the plate voltage to a higher voltage at least partially in response to the apparatus entering into the power off mode such that the storage node voltage adjusts to a voltage greater than the reference voltage.
6. The apparatus of claim 1 , further comprising a clamp to clamp the bias voltage to the reference voltage after the time delay.
7. The apparatus of claim 1 , comprising capacitance connected to an output of the first voltage generator to control the rate at which the bias voltage rises to the reference voltage.
8. The apparatus of claim 6 , comprising capacitance coupled to an output of the first voltage generator to control the rate at which the bias voltage rises to the reference voltage.
9. A method comprising:
initiating a power off mode in a memory circuit, the memory circuit comprising at least one dynamic random access memory (DRAM) cell;
maintaining a bias voltage of an access device at less than or equal to a voltage of a storage node of the memory circuit; setting a plate voltage in the memory circuit to a voltage level higher than half of a supply voltage of the memory circuit; and clamping the bias voltage to the reference voltage level after a time delay.
10. The method of claim 9 , comprising:
setting a generator signal in the memory circuit to off to provide a generator off signal.
11. The method of claim 9 , comprising:
adjusting the bias voltage to a ground level at a rate that prevents the bias voltage from exceeding the voltage of the storage node.
12. The method of claim 9 , wherein clamping the bias voltage comprises claiming the bias voltage to a ground level.
13. The method of claim 12 , comprising:
coupling the bias voltage to capacitance to control a rate at which the bias voltage rises to the ground level.
14. The method of claim 9 , wherein the bias voltage is adjusted to a ground level by a voltage regulator comprising a timing circuit to generate a desired voltage transition rate.