CMOS device and method of manufacturing same

1. A CMOS device comprising:

an NMOS transistor comprising:

a first gate electrode;

a first gate insulator under the first gate electrode, the first gate insulator defining a first gate insulator plane;

a first source region and a first drain region, both of which have a first portion below the first gate insulator plane and a second portion above the first gate insulator plane;

a first electrically insulating material above the first gate insulator plane;

a first source contact extending through the first electrically insulating material and terminating in the second portion of the first source region and a first drain contact extending through the first electrically insulating material and terminating in the second portion of the first drain region; and

a first blocking layer having a first portion between the first gate electrode and the first source contact and a second portion between the first gate electrode and the first drain contact; and

a PMOS transistor comprising:

a second gate electrode;

a second gate insulator under the second gate electrode, the second gate insulator defining a second gate insulator plane;

a second source region and a second drain region, both of which have a first portion below the second gate insulator plane and a second portion above the second gate insulator plane;

a second electrically insulating material above the second gate insulator plane;

a second source contact extending through the second electrically insulating material and terminating in the second portion of the second source region and a second drain contact extending through the second electrically insulating material and terminating in the second portion of the second drain region; and

a second blocking layer having a first portion between the second source region and the second electrically insulating material and a second portion between the second drain region and the second electrically insulating material.

2. The CMOS device of claim 1 wherein:

the second portion of the first source region and the second portion of the first drain region comprise an epitaxial semiconducting layer.

3. The CMOS device of claim 2 wherein:

the epitaxial semiconducting layer has a thickness between approximately 5 nm and approximately 30 nm.

4. The CMOS device of claim 1 wherein:

the first blocking layer and the second blocking layer comprise one of silicon-carbide and silicon-nitride.

5. The CMOS device of claim 4 wherein:

the first blocking layer and the second blocking layer have a thickness between approximately 3 nm and approximately 10 nm.

6. The CMOS device of claim 1 further comprising:

a first salicide region in the second portion of the first source region, a second salicide region in the second portion of the first drain region, a third salicide region in the second portion of the second source region, and a fourth salicide region in the second portion of the second drain region,

wherein:

the first source contact terminates on the first salicide region;

the first drain contact terminates on the second salicide region;

the second source contact terminates on the third salicide region; and

the second drain contact terminates on the fourth salicide region.

7. The CMOS device of claim 1 wherein:

the first gate insulator plane and the second gate insulator plane are substantially identical.

8. A method of manufacturing a CMOS device, the method comprising:

providing a substrate;

providing a PMOS structure comprising PMOS source/drain electrodes in PMOS source/drain regions and a PMOS extension region, all of which are at least partially located within the substrate, a first gate insulator over the substrate, and a first gate electrode over the first gate insulator, wherein the first gate insulator defines a first gate insulator plane;

providing an NMOS structure comprising NMOS source/drain regions, an NMOS extension region in the substrate, a second gate insulator over the substrate, and a second gate electrode over the second gate insulator, wherein the second gate insulator defines a second gate insulator plane;

depositing a blocking layer over the PMOS structure and the NMOS structure;

removing portions of the blocking layer such that the NMOS source/drain regions are exposed;

depositing an epitaxial semiconducting layer over the NMOS source/drain regions and over the NMOS extension region such that a surface of the epitaxial semiconducting layer is above the second gate insulator plane;

forming source/drain electrodes in the NMOS source/drain regions above the second gate insulator plane; and

forming source/drain contacts to the NMOS and PMOS source/drain electrodes.

9. The method of claim 8 wherein:

depositing the blocking layer comprises depositing one of a silicon-carbide layer and a silicon-nitride layer.

10. The method of claim 8 wherein:

removing portions of the blocking layer comprises:

depositing a photo-resist over the PMOS structure and the NMOS structure;

removing the photo-resist from the NMOS structure; and

etching the portions of the blocking layer overlying the NMOS source/drain regions using a dry etch procedure.

11. The method of claim 10 wherein:

etching the portions of the blocking layer comprises using an etch chemistry comprising at least one of carbon tetrafluoride and trifluoromethane.

12. The method of claim 8 wherein:

depositing the epitaxial semiconducting layer comprises depositing a silicon layer at a deposition temperature between approximately 700° C. and approximately 800° C.

13. The method of claim 12 wherein:

depositing the epitaxial semiconducting layer comprises depositing the silicon layer such that it has a thickness between approximately 5 nm and approximately 30 nm.

14. The method of claim 8 further comprising:

forming salicide regions in the PMOS source/drain regions above the first gate insulator plane and in the NMOS source/drain regions above the second gate insulator plane such that each one of the source/drain contacts terminates on one of the salicide regions.

15. The method of claim 8 wherein:

the first gate insulator plane and the second gate insulator plane are substantially identical.

16. A method of manufacturing a CMOS device, the method comprising:

providing a substrate;

forming a first gate insulator over the substrate, the first gate insulator defining a first gate insulator plane;

forming a first sacrificial gate over the first gate insulator, forming a first gate hard mask over the first sacrificial gate, and forming a first set of sidewall spacers adjacent to sidewalls of the first sacrificial gate;

forming PMOS source/drain electrodes in PMOS source/drain regions and a PMOS extension region such that they are at least partially located within the substrate;

forming a second gate insulator over the substrate, the second gate insulator defining a second gate insulator plane;

forming a second sacrificial gate over the second gate insulator, forming a second gate hard mask over the second sacrificial gate, and forming a second set of sidewall spacers adjacent to sidewalls of the second sacrificial gate;

forming NMOS source/drain regions and an NMOS extension region in the substrate;

forming a blocking layer over the PMOS source/drain electrodes, the PMOS extension region, the first gate hard mask, and the first set of sidewall spacers;

depositing a silicon layer over the NMOS source/drain regions and over the NMOS extension region such that a surface of the silicon layer is above the second gate insulator plane;

removing the first gate hard mask, the first sacrificial gate, the second gate hard mask, and the second sacrificial gate and forming a first gate electrode over the first gate insulator and forming a second gate electrode over the second gate insulator;

forming source/drain electrodes in the NMOS source/drain regions above the second gate insulator plane;

forming salicide regions in the PMOS source/drain regions above the first gate insulator plane and in the NMOS source/drain regions above the second gate insulator plane; and

forming source/drain contacts to the NMOS and PMOS source/drain electrodes such that each one of the source/drain contacts terminates on one of the salicide regions.

17. The method of claim 16 wherein:

the silicon layer is deposited at a deposition temperature between approximately 700° C. and approximately 800° C.

18. The method of claim 16 wherein:

the silicon layer is deposited such that it has a thickness between approximately 5 nm and approximately 30 nm.

19. The method of claim 16 wherein:

the first gate insulator plane and the second gate insulator plane are substantially identical.

20. The method of claim 16 wherein:

forming source/drain electrodes in the NMOS source/drain regions comprises:

implanting the NMOS source/drain regions with an n-type dopant; and

annealing the NMOS source/drain regions.