IP Library › Granted Patent US 7,663,522
Granted Patent B2
US 7,663,522 · App. 12/073,325 · Granted Feb 16, 2010

Performance of A/D converter and receiver

Assignee: Nokia Corporation
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Quick Facts
Patent No.
US 7,663,522
App. No.
12/073,325
Granted
Feb 16, 2010
Kind
B2
Abstract

A delta-sigma A/D converter includes a D/A converter realized with a mixed-mode comb filter connected in a feedback loop from the output of the A/D converter to the input of the A/D converter. The D/A converter is configured to predistort a feedback signal. The converter further includes an analogue filter at the input of the A/D converter. The analogue filter is configured to cancel the predistortion of the feedback signal.

Claims (43)

1. An apparatus, comprising:

a digital to analog converter realized with a mixed-mode comb filter connected in a feedback loop from an output of an analog to digital converter to an input of the analog to digital converter, wherein the digital to analog converter is configured to predistort a feedback signal; and

an analogue filter at the input of the analog to digital converter, wherein the analogue filter is configured to cancel the predistortion of the feedback signal.

2. The apparatus of claim 1 , wherein transfer functions of the mixed-mode comb filter and the analogue filter cancel each other out at frequencies below a corner frequency of a signal transfer function of the analog to digital converter.

3. The apparatus of claim 1 , wherein the mixed-mode comb filter comprises a first current-output digital to analog converter connected in parallel with a delay element and a second current-output digital to analog converter.

4. The apparatus of claim 1 , wherein the mixed-mode comb filter comprises a first voltage-output digital to analog converter with analogue summing connected in parallel with a delay element and a second voltage-output digital to analog converter with opposite output polarity and analogue summing.

5. The apparatus of claim 1 , wherein the mixed-mode comb filter comprises N digital to analog converters with an analogue summing connected to construct a first N tap averaging finite impulse response filter, the filter connected in parallel with a delay element and N digital to analog converters with the analogue summing connected to construct a second N tap averaging a finite impulse response filter, where N is an integer larger than one.

6. The apparatus of claim 5 , wherein the N digital to analog converters of the first N tap averaging finite impulse response filter have equal current output levels and the N digital to analog converters of the second N tap averaging finite impulse response filter have equal current output levels.

7. The apparatus of claim 5 , wherein the N current-output digital to analog converters of the first N tap averaging finite impulse response filter and the N current-output digital to analog converters of the second N tap averaging finite impulse response filter have nonequal current output levels and opposite current direction.

8. The apparatus of claim 1 , wherein the analogue filter is a resistor-capacitor circuit.

9. A method, comprising:

predistorting a signal of a feedback loop of a delta-sigma analog to digital converter with a digital to analog converter realized with a mixed-mode comb filter; and

canceling a predistortion and filtering an input signal of the analog to digital converter with an analogue filter at an input of the analog to digital converter.

10. The method of claim 9 , wherein transfer functions of the mixed-mode comb filter and the analogue filter cancel each other out at frequencies below a corner frequency of a signal transfer function of the delta-sigma analog to digital converter.

11. The method of claim 9 , further comprising:

predistorting the signal of the feedback loop with a first current-output digital to analog converter connected in parallel with a delay element and a second current-output digital to analog converter.

12. The method of claim 9 , further comprising:

predistorting the signal of the feedback loop with a first voltage-output digital to analog converter with analogue summing connected in parallel with a delay element and a second voltage-output digital to analog converter with opposite output polarity and analogue summing.

13. The method of claim 9 , further comprising:

predistorting the signal of the feedback loop with N current-output digital to analog converters connected to construct a first N tap averaging finite impulse response filter, the filter connected in parallel with a delay element and N current-output digital to analog converters connected to construct a second N tap averaging finite impulse response filter, where N is an integer larger than one.

14. The method of claim 9 , further comprising:

predistorting the signal of the feedback loop with N voltage-output digital to analog converters connected together with an analogue summing to construct a first N tap averaging finite impulse response filter, the filter connected in parallel with a delay element and N voltage-output digital to analog converters with opposite output polarity connected together with the analogue summing to construct a second N tap averaging finite impulse response filter, where N is an integer larger than one.

15. An apparatus, comprising:

a first circuitry and a second circuitry connected in series, wherein

the first circuitry comprises a transconductance amplifier, and a switching circuitry and an impedance circuit connected in series, wherein an input to the first circuitry is an analog signal, and

the second circuitry comprising a transconductance amplifier, and a switching circuitry connected in series, wherein an input to the second circuitry is an output signal of the transconductance amplifier of the first circuitry;

two delta-sigma analog to digital converters comprising at least two integrator stages, connected to the switching circuitry of the second circuitry; and

two feedback mixed-mode digital to analog converters, whose inputs are connected to an output of the delta-sigma analog to digital converters and an output between the switching circuitry and the impedance circuit of the first circuitry, wherein

the switching circuitry of the first circuitry is configured to switch the impedance of the impedance circuit of the first circuitry from base band to a local oscillator frequency,

the second circuitry is configured to perform quadrature down-mixing from the local oscillator frequency to the base band, and

the switching circuitry and the impedance circuit of the first circuitry are configured to up-convert a signal from the two feedback mixed-mode digital to analog converters to the local oscillator frequency.

16. An apparatus, comprising:

digital to analog converting means realized with a mixed-mode comb filter connected in a feedback loop from an output of an analog to digital converting means to an input of the analog to digital converting means, the digital to analog converting means for predistorting a feedback signal; and

analogue filtering means at the input of the analog to digital converting means, the analogue filtering means for canceling the predistortion of the feedback signal.

17. An apparatus, comprising:

first circuitry means and second circuitry means connected in series, wherein

the first circuitry means comprises a transconductance amplifier, and a switching means and an impedance means connected in series, wherein an input to the first circuitry means is an analog signal, and

the second circuitry means comprising a transconductance amplifying means, and a switching means connected in series, wherein an input to the second circuitry means is an output signal of the transconductance amplifying means of the first circuitry means;

two delta-sigma analog to digital converting means comprising at least two integrator stages, connected to the switching means of the second circuitry means; and

two feedback mixed-mode digital to analog converting means, whose inputs are connected to an output of the delta-sigma analog to digital converting means and an output between the switching means and the impedance means of the first circuitry means,

the switching means of the first circuitry means for switching the impedance of the impedance circuit of the first circuitry means from base band to a local oscillator frequency,

the second circuitry means for performing quadrature down-mixing from the local oscillator frequency to the base band, and

the switching means and the impedance means of the first circuitry means for up-converting a signal from the two feedback mixed-mode digital to analog converting means to the local oscillator frequency.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Jun 3, 2021
From: TERRIER SSC, LLC
To: WSOU INVESTMENTS, LLC
Reel/Frame 056526/0093 →
SECURITY INTEREST Recorded Jun 1, 2021
From: WSOU INVESTMENTS, LLC
To: OT WSOU TERRIER HOLDINGS, LLC
Reel/Frame 056990/0081 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: OCO OPPORTUNITIES MASTER FUND, L.P. (F/K/A OMEGA CREDIT OPPORTUNITIES MASTER FUND LP
To: WSOU INVESTMENTS, LLC
Reel/Frame 049246/0405 →
SECURITY INTEREST Recorded May 20, 2019
From: WSOU INVESTMENTS, LLC
To: BP FUNDING TRUST, SERIES SPL-VI
Reel/Frame 049235/0068 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2017
From: NOKIA TECHNOLOGIES OY
To: WSOU INVESTMENTS, LLC
Reel/Frame 043953/0822 →
SECURITY INTEREST Recorded Sep 21, 2017
From: WSOU INVESTMENTS, LLC
To: OMEGA CREDIT OPPORTUNITIES MASTER FUND, LP
Reel/Frame 043966/0574 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2015
From: NOKIA CORPORATION
To: NOKIA TECHNOLOGIES OY
Reel/Frame 035561/0460 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2008
From: KOLI, KIMMO
To: NOKIA CORPORATION
Reel/Frame 021159/0476 →
Priority Claims (1)
FI 20075299 · Apr 30, 2007 · national
Continuity (1)
Related Publication 20080278360A1 · Nov 13, 2008