Nanosilicon semiconductor substrate manufacturing method and semiconductor circuit device using nanosilicon semiconductor substrate manufactured by the method
This invention provides a substrate structure capable of controlling the threshold voltage of a MOS transistor independently of the substrate concentration and easily suppressing a short channel effect caused by reducing the channel length. A first nanosilicon film formed from nanosilicon grains having the same grain size is formed on a silicon oxide film on the surface of a silicon substrate. A silicon nitride film is formed on the first nanosilicon film. Then, a second nanosilicon film having an average grain size different from that of the first nanosilicon film is formed. A semiconductor circuit device is formed on a thus manufactured nanosilicon semiconductor substrate.
1. A method of manufacturing a nanosilicon semiconductor substrate by forming a nanosilicon film on a substrate by repeating steps of depositing a single nanosilicon layer formed from nanosilicon grains and forming an insulating film on a surface of each nanosilicon grain, the method comprising:
a first step of forming, on the substrate, a first nanosilicon film formed from a plurality of nanosilicon grains; and
a second step of forming, on the first nanosilicon film, a second nanosilicon film formed from a plurality of nanosilicon grains which have an average grain size different from that of the plurality of nanosilicon grains contained in the first nanosilicon film.
2. The method according to claim 1 , wherein annealing is performed at not less than 800° C. after formation of the first nanosilicon film and the second nanosilicon film.
3. The method according to claim 2 , wherein the annealing is performed in one of a hydrogen atmosphere and an atmosphere containing a hydrogen radical dissociated from hydrogen.
4. The method according to claim 1 , wherein an insulating film is deposited between the first nanosilicon film and the second nanosilicon film which have different average grain sizes.
5. The method according to claim 1 , wherein a grain size fluctuation with respect to the average grain size of the nanosilicon grains of the first nanosilicon film and the second nanosilicon film is not more than 1 nm.
6. A semiconductor circuit device including a circuit element formed on a nanosilicon semiconductor substrate manufactured by a nanosilicon semiconductor substrate manufacturing method of claim 1 .
7. The device according to claim 6 , wherein a MOS transistor is formed on each of nanosilicon films which have different average grain sizes and are selectively exposed on the nanosilicon semiconductor substrate.
8. The device according to claim 7 , wherein nanosilicon grains contained in each nanosilicon film have a bandgap energy corresponding to a grain size so that the MOS transistors formed on the nanosilicon films having the different average grain sizes have different threshold voltages (VT).