IP Library › Granted Patent US 7,683,397
Granted Patent B2
US 7,683,397 · App. 11/490,994 · Granted Mar 23, 2010

Semi-planar avalanche photodiode

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,683,397
App. No.
11/490,994
Granted
Mar 23, 2010
Kind
B2
Abstract

An avalanche photodetector is disclosed. An apparatus according to aspects of the present invention includes a mesa structure defined in a first type of semiconductor. The first type of semiconductor material includes an absorption region optically coupled to receive and absorb an optical beam. The apparatus also includes a planar region proximate to and separate from the mesa structure and defined in a second type of semiconductor material. The planar region includes a multiplication region including a p doped region adjoining an n doped region to create a high electric field in the multiplication region. The high electric field is to multiply charge carriers photo-generated in response to the absorption of the optical beam received in the mesa structure.

Claims (10)

1. An apparatus, comprising:

a mesa structure defined in a first type of semiconductor, the first type of semiconductor material including an absorption region optically coupled to receive and absorb an optical beam; and

a planar region proximate to and separate from the mesa structure and defined in a second type of semiconductor material, the planar region including a multiplication region including a p doped region adjoining an n doped region to create a high electric field in the multiplication region to multiply charge carriers photo-generated in response to the absorption of the optical beam received in the mesa structure,

wherein the planar region further includes a guard ring structure disposed in the second type of semiconductor material of the planar region surrounding the mesa structure,

wherein the guard ring structure is a floating guard ring at an interface between the absorption region and the multiplication region.

2. The apparatus of claim 1 wherein the first type of semiconductor comprises germanium and the second type of semiconductor material comprises silicon.

3. The apparatus of claim 1 wherein the first type of semiconductor comprises InGaAs and the second type of semiconductor material comprises silicon.

4. The apparatus of claim 1 wherein the guard ring structure is a floating guard ring including p doped second type of semiconductor material.

5. The apparatus of claim 1 further comprising contacts coupled to the mesa structure and planar regions, respectively, to receive an external bias voltage to create a low electric field in the mesa structure.

6. The apparatus of claim 5 further comprising a p doped region in the mesa structure and a second n doped region in the planar region coupled to the contacts.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2008
From: SARID, GADI; KANG, YIMIN; PAUCHARD, ALEXANDRE
To: INTEL CORPORATION
Reel/Frame 020421/0585 →
Continuity (1)
Related Publication 20080017883A1 · Jan 24, 2008