IP Library › Granted Patent US 7,683,463
Granted Patent B2
US 7,683,463 · App. 11/737,630 · Granted Mar 23, 2010

Etched leadframe structure including recesses

Assignee: Fairchild Semiconductor Corporation
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Quick Facts
Patent No.
US 7,683,463
App. No.
11/737,630
Granted
Mar 23, 2010
Kind
B2
Abstract

A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess.

Claims (41)

1. A leadframe structure comprising:

a first leadframe structure portion comprising a first thin portion and a first thick portion, wherein the first thin portion is defined in part by a first recess; and

a second leadframe structure portion comprising a second thin portion and a second thick portion, wherein the second thin portion is defined in part by a second recess;

wherein the first thin portion faces the second recess, and the second thin portion faces the first recess, wherein a thickness of the first thin portion is less than 50% of the thickness of the first thick portion.

2. The leadframe structure of claim 1 wherein the first leadframe structure portion comprises a lead, and wherein the second leadframe structure portion comprises a die attach pad.

3. The leadframe structure of claim 1 wherein the leadframe structure comprises copper.

4. The leadframe structure of claim 1 wherein a thickness of the second thin portion is less than 50% of the thickness of the second thick portion.

5. The leadframe structure of claim 1 wherein the first recess and the second recess are formed by etching.

6. A semiconductor die package comprising:

the leadframe structure of claim 1 ; and

a semiconductor die mounted on the second leadframe structure portion.

7. A semiconductor die package comprising:

a leadframe structure comprising a first leadframe structure portion comprising a first thin portion and a first thick portion, wherein the first thin portion is defined in part by a first recess, wherein the first leadframe structure portion is a lead, and a second leadframe structure portion comprising a second thin portion and a second thick portion, wherein the second thin portion is defined in part by a second recess, and wherein the second leadframe structure portion is a die attach pad, wherein the first thin portion faces the second recess, and the second thin portion faces the first recess, wherein a thickness of the first thin portion is less than 50% of the thickness of the first thick portion;

a semiconductor die on the die attach pad; and

a molding material formed around at least part of the leadframe structure and the semiconductor die.

8. The semiconductor die package of claim 7 wherein the semiconductor die comprises a power transistor.

9. The semiconductor die package of claim 7 wherein the semiconductor die comprises a vertical power transistor.

10. The semiconductor die package of claim 7 further comprising a wirebond formed between the semiconductor die and the lead.

11. An electrical assembly comprising the semiconductor die package of claim 10 .

12. The leadframe structure of claim 1 wherein the first leadframe structure portion includes a first surface and a second surface opposite the first surface, where the first surface of the first leadframe structure portion and the second surface of the first leadframe structure portion define the first thick portion, and wherein the first thin portion is also defined in part by the second surface of the first leadframe structure portion.

13. The leadframe structure of claim 12 wherein the second leadframe structure portion includes a first surface and a second surface opposite the first surface, where the first surface of the second leadframe structure portion and the second surface of the second leadframe structure portion define the second thick portion, and wherein the second thin portion is also defined by the first surface of the second leadframe structure portion.

14. The leadframe structure of claim 13 wherein the first thick portion and the second thick portion have the same thickness.

15. The leadframe structure of claim 14 wherein a distance between the first thin portion and the second thin portion is about 50% of the thickness of the first thick portion.

16. The leadframe structure of claim 1 wherein lengths of the first thin portion and the second thin portion are less than 20 mils.

17. A leadframe structure comprising:

a first leadframe structure portion comprising a first thin portion and a first thick portion, wherein the first thin portion is defined in part by a first recess; and

a second leadframe structure portion comprising a second thin portion and a second thick portion, wherein the second thin portion is defined in part by a second recess;

wherein the first thin portion faces the second recess, and the second thin portion faces the first recess, wherein the first thin portion and the second thin portion vertically overlap with respect to each other, but are electrically isolated from each other.

18. The electrical assembly of claim 11 further comprising a circuit substrate; and the semiconductor die package mounted to the circuit substrate.

19. The leadframe structure of claim 17 wherein the leadframe structure consists of copper.

20. The leadframe structure of claim 17 wherein the first leadframe structure portion comprises a lead, and wherein the second leadframe structure portion comprises a die attach pad.

21. The leadframe structure of claim 17 wherein the leadframe structure comprises copper.

22. The leadframe structure of claim 17 wherein a thickness of the first thin portion is less than 50% of the thickness of the first thick portion.

23. The leadframe structure of claim 17 wherein a thickness of the second thin portion is less than 50% of the thickness of the second thick portion.

24. The leadframe structure of claim 17 wherein the first recess and the second recess are formed by etching.

25. A semiconductor die package comprising:

a leadframe structure comprising a first leadframe structure portion comprising a first thin portion and a first thick portion, wherein the first thin portion is defined in part by a first recess, wherein the first leadframe structure portion is a lead, and a second leadframe structure portion comprising a second thin portion and a second thick portion, wherein the second thin portion is defined in part by a second recess, and wherein the second leadframe structure portion is a die attach pad, wherein the first thin portion faces the second recess, and the second thin portion faces the first recess, wherein the first thin portion and the second thin portion vertically overlap with respect to each other, but are electrically isolated from each other;

a semiconductor die on the die attach pad; and

a molding material formed around at least part of the leadframe structure and the semiconductor die.

26. The semiconductor die package of claim 25 wherein the semiconductor die comprises a vertical power MOSFET.

27. An electrical assembly comprising the semiconductor die package of claim 25 .

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2008
From: LIM, LAY YEAP
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 020849/0308 →
Continuity (1)
Related Publication 20080258272A1 · Oct 23, 2008