Method and apparatus to align and standardize packet based parallel interfaces
A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.
1. A packet alignment system, comprising:
at least one register for receiving an input signal comprising a control signal and a data signal;
an aligner connected to the at least one register, the aligner configured to receive the input signal from the at least one register when the input signal comprises a data word of a predetermined size and cyclically shift said data word of a predetermined size to form a plurality of shifted data words;
a plurality of pipe registers for collecting the plurality of shifted data words, each one of said plurality of pipe registers configured to generate an adjusted control signal for each one of said plurality of shifted data words;
a filtering logic for identifying one of the plurality of shifted data words as a desired aligned data word, and for registering header data contained in the desired aligned data word in a header register, registering payload data contained in the desired aligned data word in a payload register, and registering end-to-end cyclic redundancy check (ECRC) data contained in the desired aligned data word in an ECRC register;
an output interface for generating an outgoing signal and providing data from at least one of the header register, the payload register and the ECRC register.
2. The packet alignment system of claim 1 , wherein the control signal comprises at least one of a Start-of-Packet (SOP) position, an End-of-Packet (EOP) position, a data valid indicator, and an error indicator.
3. The packet alignment system of claim 1 , wherein the data signal comprises at least one of an incoming header data, an incoming payload data, and an incoming ECRC data.
4. The packet alignment system of claim 1 , wherein the outgoing signal comprises at least one of an SOP present signal, an EOP present signal, an EOP position, a payload valid signal, and an error signal.
5. The packet alignment system of claim 1 , wherein the filtering logic further comprises an error handling logic for detecting possible errors in a packet, and wherein erroneous packet data is discarded automatically by the filtering logic.
6. The packet alignment system of claim 1 , wherein the filtering logic further comprises an error handling logic for detecting possible errors in a packet, and wherein erroneous packet data is indicated in the outgoing signal.
7. The packet alignment system of claim 1 , wherein the aligner is a barrel shift aligner.
8. A packet alignment system, comprising:
at least one register for receiving an input signal comprising a control signal and a data signal;
an aligner connected to the at least one register, the aligner configured to receive the input signal from the at least one register when the input signal comprises a data word of a predetermined size and cyclically shift said data word of a predetermined size to form a plurality of shifted data words;
means for collecting the plurality of shifted data words, the collecting means configured to generate an adjusted control signal for each one of said plurality of shifted data words;
means for identifying one of the plurality of shifted data words as a desired aligned data word;
means for registering header data contained in the desired aligned data word in a header register, registering payload data contained in the desired aligned data word in a payload register, and registering end-to-end cyclic redundancy check (ECRC) data contained in the desired aligned data word in an ECRC register; and
an output interface for generating an outgoing signal and providing data from at least one of the header register, the payload register and the ECRC register.
9. The packet alignment system of claim 8 , wherein the control signal comprises at least one of a Start-of-Packet (SOP) position, an End-of-Packet (EOP) position, a data valid indicator, and an error indicator.
10. The packet alignment system of claim 8 , wherein the data signal comprises at least one of an incoming header data, an incoming payload data, and an incoming ECRC data.
11. The packet alignment system of claim 8 , wherein the outgoing signal comprises at least one of an SOP present signal, an EOP present signal, an EOP position, a payload valid signal, and an error signal.
12. The packet alignment system of claim 8 , wherein the aligning means further comprises an error handling logic for detecting possible errors in a packet, and wherein erroneous packet data is discarded automatically by the filtering logic.
13. The packet alignment system of claim 8 , wherein the aligning means further comprising an error handling logic for detecting possible errors in a packet, and wherein erroneous packet data is indicated in the outgoing signal.
14. The packet alignment system of claim 8 , wherein the aligner is a barrel shift aligner.
15. A packet alignment method, comprising:
receiving an input signal, the input signal comprising a control signal and a data signal;
supplying the input signal to an aligner when the input signal comprises a data word of a predetermined size;
triggering the aligner to cyclically shift said data word of a predetermined size to form a plurality of shifted data words;
collecting the plurality of shifted data words;
generating an adjusted control signal for each one of said plurality of shifted data words; identifying one of the plurality of shifted data words as a desired aligned data word;
registering header data contained in the desired aligned data word in a header register;
registering payload data contained in the desired aligned data word in a payload register;
registering end-to-end cyclic redundancy check (ECRC) data contained in the desired aligned data word in an ECRC register; and
generating an outgoing signal.
16. The packet alignment method of claim 15 , wherein the control signal comprises at least one of a Start-of-Packet (SOP) position, an End-of-Packet (EOP) position, a data valid indicator, and an error indicator.
17. The packet alignment method of claim 15 , wherein the data signal comprises at least one of an incoming header data, an incoming payload data, and an incoming ECRC data.
18. The packet alignment method of claim 15 , wherein the outgoing signal comprises at least one of an SOP present signal, an EOP present signal, an EOP position, a payload valid signal, and an error signal.
19. The packet alignment method of claim 15 , further comprising detecting possible errors in a packet, wherein erroneous packet data is discarded automatically.
20. The packet alignment method of claim 15 , further comprising detecting possible errors in a packet, wherein erroneous packet data is indicated in the outgoing signal.