IP Library Granted Patent US 7,705,570
Granted Patent B2
US 7,705,570 · App. 12/359,991 · Granted Apr 27, 2010

Power supply output voltage trimming

Assignee: Power Integrations, Inc.
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Quick Facts
Patent No.
US 7,705,570
App. No.
12/359,991
Granted
Apr 27, 2010
Kind
B2
Abstract

A power supply trim control signal is produced by integrating differences between monitored and target values of the output voltage of a power supply. Register storage requirements are reduced by producing the target value from a nominal voltage value and one of a plurality of margin offsets selected in accordance with control data. The control data also selects between open and closed loop trim control. Stability is enhanced by changing the target value slowly in response to any change in the control data.

Claims (18)

1. An apparatus for trimming an output voltage of a power supply, the apparatus comprising:

a non-volatile store for storing values representing a nominal value of the output voltage, a plurality of margin values, and control data; and

a control unit comprising:

means for selecting, in dependence upon the control data, one of the plurality of margin values stored in the non-volatile store;

means for combining the selected one of the plurality of margin values with the nominal value of the output voltage stored in the non-volatile store to produce a target value of the output voltage;

a register for storing the target value;

means for monitoring the output voltage of the power supply;

means for integrating differences between monitored values of the output voltage and the target value to produce a control signal; and

means for supplying the control signal to a trim input of the power supply to trim the output voltage of the power supply to reduce said differences.

2. An apparatus as claimed in claim 1 wherein said values are digital values, the apparatus further comprising:

means for converting the monitored output voltage to a digital value; and

means for converting a digital value representing the control signal to an analog signal.

3. An apparatus as claimed in claim 2 wherein the means for integrating differences comprises:

an arithmetic logic unit for forming said differences; and

an accumulator having less significant bit positions for accumulating the differences and more significant bit positions from which the control signal is derived.

4. An apparatus as claimed in claim 2 wherein the means for combining the selected one of the margin values with the nominal value of the output voltage to produce a target value of the output voltage is responsive to a change of the control data to make any change of the target value gradually at a slow rate.

5. An apparatus method as claimed in claim 2 wherein the control unit further comprises:

means, responsive to an indication of open loop control in the control data, for producing the control signal from the selected one of the plurality of margin values instead of integrating differences between monitored values of the output voltage and the target value, and for supplying the nominal value of the output voltage as the target value of the output voltage.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2009
From: POTENTIA SEMICONDUCTOR, INC.
To: POTENTIA SEMICONDUCTOR CORP.
Reel/Frame 023390/0397 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2009
From: POWER INTEGRATIONS, LTD.
To: POWER INTEGRATIONS, INC.
Reel/Frame 023390/0406 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2009
From: POTENTIA SEMICONDUCTOR CORPORATION
To: POWER INTEGRATIONS LTD.
Reel/Frame 023390/0420 →
Continuity (2)
Continuation 1116962900 · Jun 30, 2005
Related Publication 20090128114A1 · May 21, 2009