Cell array of memory device sharing selection line
A cell array of a flash memory device includes a memory cell transistor connected to a word line, a first selection transistor for controlling a first connection between the memory cell transistor and a bit line in response to a selection signal, and a second selection transistor for controlling a second connection between the memory cell transistor and a common source line in response to the selection signal.
1. A cell array structure of a flash memory device, comprising:
a memory cell transistor connected to a word line;
a first selection transistor for controlling a first connection between the memory cell transistor and a bit line in response to a selection signal; and
a second selection transistor for controlling a second connection between the memory cell transistor and a common source line in response to the selection signal,
wherein the selection signal is supplied to a first gate line of the first selection transistor and a second gate line of the second selection transistor, the first gate line and the second gate line being connected by a local interconnection.
2. The cell array structure of claim 1 , wherein the word line comprises a gate line of the memory cell transistor.
3. The cell array structure of claim 2 , further comprising:
a first strapping line positioned on the word line and electrically connected to the word line.
4. The cell array structure of claim 3 , further comprising:
a second strapping line positioned on one of the first gate line and the second gate line, and electrically connected to the one of the first gate line and the second gate line.
5. The cell array structure of claim 4 , further comprising:
a third strapping line positioned on and connected to a diffusion layer in which the common source line is located.
6. The cell array structure of claim 3 , wherein the local interconnection is positioned on a different conduction layer than the first strapping line.
7. The cell array structure of claim 1 , further comprising:
a first switch for supplying a word line voltage to the word line; and
a second switch for supplying the selection signal to the first gate line of the first selection transistor and to the second gate line of the second selection transistor.
8. A flash memory device, comprising:
a first switch for supplying a selection signal to a selection signal line;
a second switch for supplying a word line voltage to a word line;
a memory cell transistor connected to the word line;
a first selection transistor, connected to the selection signal line, for controlling a first connection between the memory cell transistor and a bit line in response to the selection signal; and
a second selection transistor, connected to the selection signal line, for controlling a second connection between the memory cell transistor and a common source line in response to the selection signal,
wherein the selection signal line comprises a first gate line of the first selection transistor and a second gate line of the second selection transistor, the first gate line and the second gate line being electrically connected to each other by a local interconnection.
9. The flash memory device of claim 8 , wherein one of the first gate line and the second gate line is electrically connected to a first strapping line.
10. The flash memory device of claim 9 wherein the word line is electrically connected to a second strapping line.
11. The flash memory device of claim 10 , wherein the common source line is electrically connected to a third strapping line.
12. The flash memory device of claim 8 , wherein the local interconnection extends in a direction of the bit line.
13. The flash memory device of claim 8 , wherein the local interconnection is positioned on a conduction layer different from a conduction layer of the first strapping line.
14. A cell array structure of a flash memory device, comprising:
a plurality of memory cell units arranged in rows and columns, each memory cell unit comprising a first selection transistor, a memory cell transistor and a second selection transistor, connected in series between a corresponding column and a common source line, a first gate line of the first selection transistor being electrically connected to a second gate line of the second selection transistor by a local interconnection.
15. The cell array structure of claim 14 , further comprising:
a first strapping line positioned on one of the first gate line and the second gate line, and electrically connected to the one of the first gate line and the second gate line.
16. The cell array structure of claim 15 , further comprising:
a second strapping line positioned on a gate line of the memory cell transistor and electrically connected to the gate line of the memory cell transistor.
17. The cell array structure of claim 16 , further comprising:
a third strapping line positioned on and electrically connected to a diffusion layer in which the common source line is positioned.
18. The cell array structure of claim 14 , wherein the local interconnection is located on a conduction layer different from a conduction layer of the first strapping line.
19. The cell array structure of claim 14 , further comprising:
a first switch for supplying a word line voltage to a word line of the memory cell transistor; and
a second switch for supplying a selection signal to the first gate line of the first selection transistor and the second gate line of the second selection transistor.