Method for improved power distribution in a three dimensional vertical integrated circuit
View Patent ↗A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path.
1. A method of manufacture for a microelectronic device comprising:
etching a first hole defined by a first wall at least partly through a substrate of a first chip;
forming a layer of electrically insulating material to cover the first wall;
etching a second hole defined by a second wall at least partly through the substrate of the first chip;
forming electrically conductive material within the first hole and the second hole; and
providing a second chip to be in electrical contact with the first chip;
wherein a first voltage supply may be transferred from the first chin to the second chip via the electrically conductive material in the second hole and via the substrate surrounding the electrically conductive material in the second hole.
2. The method of claim 1 wherein the electrically conductive material in the first hole is electrically insulated from the substrate of the first chip and the electrically conductive material in the second hole is not electrically insulated from the substrate of the first chip.
3. The method of claim 1 wherein a second voltage supply is electrically transferred from the first chip to the second chip via the electrically conductive material in the first hole and not via the substrate surrounding the electrically conductive material in the first hole.
4. The method of claim 3 wherein the first supply voltage is Vdd and the second supply voltage is GND.
5. The method of claim 3 wherein the first supply voltage is GND and the second supply voltage is Vdd.
6. The method of claim 1 further comprising the step of:
providing the first chip for front end of line (FEOL) or back end of line (BEOL) processes.
7. The method of claim 6 further comprising the steps of:
bonding a backside bonding layer to the backside of the first chip, the backside bonding layer comprising a plurality of electrically conductive pads each separated by electrically insulating material.
8. The method of claim 7 further comprising the step of:
providing the second chip to be in electrical contact with the first chip by bonding the second chip to the bonding layer.
9. The method of claim 1 wherein the electrically conductive material in the first hole and in the second hole is either doped polysilicon or tungsten.
10. A method of manufacture for a microelectronic device comprising:
etching a first hole defined by a first wall at least partly through a substrate of a first chip;
forming a layer of electrically insulating material to cover the first wall;
etching a second hole defined by a second wall at least partly through the substrate of the first chip;
forming electrically conductive material within the first hole and the second hole; and
providing a second chip to be in electrical contact with the first chip;
wherein a first voltage supply may be transferred from the second chip to the first chip via the electrically conductive material in the second hole and via the substrate surrounding the electrically conductive material in the second hole.
11. The method of claim 10 wherein the electrically conductive material in the first hole is electrically insulated from the substrate of the first chip and the electrically conductive material in the second hole is not electrically insulated from the substrate of the first chip.
12. The method of claim 10 wherein a second voltage supply is electrically transferred from the second chip to the first chip via the electrically conductive material in the first hole and not via the substrate surrounding the electrically conductive material in the first hole.
13. The method of claim 10 wherein the first supply voltage is Vdd and the second supply voltage is GND.
14. The method of claim 10 wherein the first supply voltage is GND and the second supply voltage is Vdd.
15. The method of claim 10 further comprising the step of:
providing the first chip for front end of line (FEOL) or back end of line (BEOL) processes.
16. The method of claim 10 further comprising the step of:
bonding a backside bonding layer to the backside of the first chip, the backside bonding layer comprising a plurality of electrically conductive pads each separated by electrically insulating material.
17. The method of claim 16 further comprising the step of:
providing the second chip to be in electrical contact with the first chip by bonding the second chip to the bonding layer.
18. The method of claim 10 wherein the electrically conductive material in the first hole and in the second hole is either doped polysilicon or tungsten.