One-transistor type DRAM
A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.
1. A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line, the DRAM comprising:
a plurality of source lines and word lines arranged in a row direction;
a plurality of bit lines arranged in a column direction;
a plurality of clamp bit lines and reference bit lines arranged in the column direction;
a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed;
a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the clamp bit line are crossed;
a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the reference bit line are crossed; and
a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.
2. The one-transistor type DRAM according to claim 1 , wherein the clamp cell array and the reference cell array are configured to store data “0”.
3. The one-transistor type DRAM according to claim 1 , wherein the cell array includes a first cell and a second cell which are connected between a first source line and a second source line and configured to have a common drain connected to the bit line and a gate connected to a different word line.
4. The one-transistor type DRAM according to claim 3 , wherein the clamp cell array includes:
first and second clamp cells connected between the first source line and the second source line and configured to have a common drain connected to the clamp bit line and a gate connected to a different word line, wherein the reference cell array includes first and second reference cells which are connected between the first source line and the second source line and configured to have a common drain connected to the reference bit line and a gate connected to a different word line.
5. The one-transistor type DRAM according to claim 1 , wherein the cell array includes a plurality of cell groups connected to the bit line, the cell groups including a first group connected to a first bit line and a second group connected to a second bit line.
6. The one-transistor type DRAM according to claim 5 , wherein the first group and the second group are alternately arranged in row and column directions.
7. The one-transistor type DRAM according to claim 5 , wherein the clamp cell array includes a plurality of clamp cell groups connected to the bit line, the clamp cell groups including a first group connected to a first clamp bit line and a second clamp group connected to a second clamp bit line.
8. The one-transistor type DRAM according to claim 5 , wherein the reference cell array includes a plurality of reference cell groups connected to the reference bit line.
9. The one-transistor type DRAM according to claim 1 , further comprising:
a reference offset current adjusting unit configured to adjust an offset current of the reference bit line;
a clamp voltage generating unit connected to the clamp bit line and configured to generate the clamp voltage; and
a reference voltage generating unit connected to the reference bit line and configured to generate the reference voltage.
10. The one-transistor type DRAM according to claim 9 , wherein a current flowing in the reference bit line includes a reference current of the cell and the offset current.
11. The one-transistor type DRAM according to claim 9 , wherein the clamp voltage generating unit includes:
a reference bias unit configured to supply a bias voltage to the clamp bit line;
a clamp voltage adjusting unit configured to output a clamp voltage control signal for adjusting the clamp voltage corresponding to a voltage value of the clamp bit line; and
a clamp voltage output unit configured to output the clamp voltage in response to the clamp voltage control signal.
12. The one-transistor type DRAM according to claim 9 , wherein the reference voltage generating unit includes:
a current sensing load unit configured to control the reference current depending on a load voltage; and
a bit line voltage bias control unit configured to control the reference voltage flowing in the reference bit line depending on the clamp voltage.