IP Library Granted Patent US 7,745,811
Granted Patent B2
US 7,745,811 · App. 11/561,365 · Granted Jun 29, 2010

Phase change memory devices and methods for fabricating the same

Assignee: Industrial Technology Research Institute
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Quick Facts
Patent No.
US 7,745,811
App. No.
11/561,365
Granted
Jun 29, 2010
Kind
B2
Abstract

Phase change memory devices and methods for fabricating the same. An exemplary phase change memory device includes a conductive element formed in a dielectric layer. A phase change material layer is formed in the dielectric layer. A conductive layer extends in the dielectric layer to respectively electrically connect the phase change layer and a sidewall of the conductive element.

Claims (40)

1. A phase change memory (PCM) device, comprising:

a semiconductor substrate;

a dielectric layer formed over the substrate;

a conductive element formed in the dielectric layer;

a phase change material layer formed in the dielectric layer; and

a conductive layer extending in the dielectric layer, wherein the conductive layer has an L-shaped top view and opposite first and second sidewalls, the first sidewall physically contacting a sidewall rather than a top or bottom wall of the phase change material layer, and the second sidewall physically contacting a sidewall rather than a top or bottom wall of the conductive element, wherein the sidewalls of the conductive layer, conductive element, and phase change material layer are perpendicular to an upper surface of the substrate.

2. The PCM device as claimed in claim 1 , wherein the conductive layer merely connects a portion of the phase change material layer.

3. The PCM device as claimed in claim 1 , wherein the phase change material layer comprises chalcogenide materials.

4. The PCM device as claimed in claim 1 , wherein the conductive layer has a spacer cross-section of a curved sidewall surface.

5. The PCM device as claimed in claim 1 , wherein the conductive layer extends horizontally in the dielectric layer.

6. A phase change memory (PCM) device, comprising:

a semiconductor substrate;

a transistor formed over the semiconductor substrate;

a first dielectric layer formed over the semiconductor substrate, covering the transistor;

a first conductive plug formed in the first dielectric layer, electrically contacting a source of the transistor;

a second dielectric layer formed over the first dielectric layer;

a second conductive plug formed in the second dielectric layer, electrically contacting the first conductive plug;

a conductive layer extending in the second dielectric layer, wherein the conductive layer has an L-shaped top view opposite and first and second sidewalls, the first sidewall physically contacting a sidewall rather than a top or bottom wall of the second conductive plug;

a third dielectric layer formed over the second dielectric layer;

a phase change material layer formed in the third and second dielectric layers, wherein the second sidewall of the conductive layer physically contacts a sidewall rather than a top or bottom wall of the phase change material layer; and

an electrode formed over the third dielectric layer, electrically connected to the phase change material layer, wherein the sidewalls of the conductive layer, the second conductive plug, and the phase change material layer are perpendicular to an upper surface of the substrate.

7. The PCM device as claimed in claim 6 , wherein the conductive layer merely connects a portion of the phase change material layer.

8. The PCM device as claimed in claim 6 , wherein the phase change material layer comprises chalcogenide materials.

9. The PCM device as claimed in claim 6 , wherein the conductive layer has a spacer cross-section of a curved sidewall surface.

10. The PCM device as claimed in claim 6 , wherein the conductive layer extends horizontally in the second dielectric layer.

11. A phase change memory (PCM) device, comprising:

a semiconductor substrate;

a pair of transistors formed over a portion of the semiconductor substrate, respectively;

a first dielectric layer formed over the semiconductor substrate, covering the transistors;

a pair of first conductive plugs formed in a portion of the first dielectric layer, respectively, electrically contacting a source of one of the transistors;

a second dielectric layer formed over the first dielectric layer;

a pair of second conductive plugs formed in a portion of the second dielectric layer, respectively, electrically contacting the first conductive plug;

a pair of conductive layers extending in a portion of the second dielectric layer, respectively, wherein the conductive layers have an L-shaped top view and opposite first and second sidewalls, the first sidewalls respectively physically contacting a sidewall rather than a top or bottom wall of the second conductive plug;

a third dielectric layer formed over the second dielectric layer;

a phase change material layer formed in the third and second dielectric layers, wherein the second sidewalls of the conductive layers physically respectively contact a sidewall rather than a top or bottom wall of the phase change material layer; and

an electrode formed over the third dielectric layer, electrically connected to the phase change material layer, wherein the sidewalls of the conductive layers, second conductive plugs, and phase change material layer are perpendicular to an upper surface of the substrate.

12. The PCM device as claimed in claim 11 , wherein the conductive layers merely connect a portion of the phase change material layer, respectively.

13. The PCM device as claimed in claim 11 , wherein the phase change material layer comprises chalcogenide materials.

14. The PCM device as claimed in claim 11 , wherein the conductive layers have a spacer cross-section of a curved sidewall surface.

15. The PCM device as claimed in claim 11 , wherein the conductive layers extend horizontally in the second dielectric layer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2011
From: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
To: HIGGS OPL. CAPITAL LLC
Reel/Frame 027364/0397 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2010
From: POWERCHIP SEMICONDUCTOR CORP.; NANYA TECHNOLOGY CORPORATION; PROMOS TECHNOLOGIES INC.; WINBOND ELECTRONICS CORP.
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Reel/Frame 024149/0102 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2006
From: LEE, HENGYUAN; CHAO, DER-SHENG
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE; POWERCHIP SEMICONDUCTOR CORP.; NANYA TECHNOLOGY CORPORATION.; PROMOS TECHNOLOGIES INC.; WINBOND ELECTRONICS CORP.
Reel/Frame 018556/0388 →
Priority Claims (1)
TW 95130066 A · Aug 16, 2006 · national
Continuity (1)
Related Publication 20080042243A1 · Feb 21, 2008