Semiconductor device
View Patent ↗A semiconductor device is disclosed. The semiconductor device provides a substrate comprising an image sensor region and a circuit region, wherein the circuit region comprises a pad region and a connecting region. A multilayer interconnect structure is formed on the substrate, wherein the multilayer interconnect structure comprises a plurality of dielectric layers, a plurality of lower wirings at the pad region and the connecting region, and a top wiring on at least one of the lower wirings at the connecting region. A passivation layer is formed over the multilayer interconnect structure. A pad structure is formed through the passivation layer and at least one of the dielectric layers on and electrically connected to at least one of the lower wirings at the pad region.
1. A semiconductor device, comprising:
a substrate comprising an image sensor region and a circuit region, wherein the circuit region comprises a pad region and a connecting region;
a multilayer interconnect structure formed on the substrate, wherein the multilayer interconnect structure comprises a plurality of dielectric layers, a plurality of lower wirings at the pad region and the connecting region, and a top wiring on at least one of the lower wirings at the connecting region;
a passivation layer formed over the multilayer interconnect structure; and
a pad structure comprising an opening formed through the passivation layer and at least one of the dielectric layers and a pad layer conformally formed in the opening and on sidewalls of the passivation layer and the dielectric layers, wherein the pad structure is on and electrically connected to at least one of the lower wirings at the pad region.
2. The semiconductor device as claimed in claim 1 , wherein the image sensor region comprises an image sensor formed on the substrate.
3. The semiconductor device as claimed in claim 1 , wherein the pad structure comprises an opening and a pad layer in the opening.
4. The semiconductor device as claimed in claim 1 , wherein a surface of the pad layer is substantially coplanar with the passivation layer.
5. The semiconductor device as claimed in claim 1 , wherein a surface of the pad layer is substantially lower than a surface of the passivation layer.
6. The semiconductor device as claimed in claim 1 , wherein the pad structure further comprises a planarization layer overlaid the passivation layer and the pad structure.
7. The semiconductor device as claimed in claim 6 , wherein the pad structure further comprising a microlens layer forming on the planarization layer.
8. The semiconductor device as claimed in claim 1 made by the process comprising steps:
providing a substrate comprising an image sensor region and a circuit region, wherein the circuit region comprises a pad region and a connecting region;
forming a multilayer interconnect structure on the substrate, wherein the multilayer interconnect structure comprises a plurality of dielectric layers, a plurality of lower wirings at the pad region and the connecting region, and a top wiring on at least one of the lower wirings at the connecting region;
forming a passivation layer over the multilayer interconnect structure; and
forming a pad structure through the passivation layer and at least one of the dielectric layers on and electrically connected to at least one of the lower wirings at the pad region.
9. A semiconductor device, comprising:
a substrate comprises an image sensor formed thereon;
a multilayer interconnect structure formed on the substrate, wherein the multilayer interconnect structure comprises a plurality of lower wirings and a top wiring;
a passivation layer formed over the multilayer interconnect structure; and
a pad structure comprising an opening formed through the passivation layer and a pad layer conformally formed in the opening and on sidewalls of the passivation layer, wherein a bottom of the pad layer is not higher than a bottom of the top wiring.
10. The semiconductor device as claimed in claim 9 , wherein a surface of the pad layer is substantially coplanar with the passivation layer.
11. The semiconductor device as claimed in claim 9 , wherein a surface of the pad layer is substantially lower than a surface of the passivation layer.
12. The semiconductor device as claimed in claim 9 , wherein the pad structure is electrically connected to at least one of the lower wirings.
13. The semiconductor device as claimed in claim 9 , wherein the pad structure further comprising a microlens layer forming on a planarization layer overlying the passivation layer and the pad layer.
14. The semiconductor device as claimed in claim 9 made by the process comprising steps:
providing a substrate comprising an image sensor formed thereon;
forming a multilayer interconnect structure on the substrate, wherein the multilayer interconnect structure comprises a plurality of lower wirings and a top wiring;
forming a passivation layer over the multilayer interconnect structure;
forming an opening through the passivation layer, wherein a bottom of the opening is lower than the top wiring; and
comformably forming a pad layer in the opening to form a pad structure.
15. A semiconductor device, comprising:
a substrate comprises an image sensor formed thereon;
a multilayer interconnect structure formed on the substrate;
a passivation layer formed over the multilayer interconnect structure; and
a pad structure comprising an opening formed through the passivation layer and a pad layer conformally formed in the opening and on sidewalls of the passivation layer, wherein a surface of the pad layer is not over the passivation layer, wherein the pad structure is directly electrically connected to a lower wiring of the multilayer interconnect structure.
16. The semiconductor device as claimed in claim 15 , wherein the surface of the pad layer is substantially coplanar with the passivation layer.
17. The semiconductor device as claimed in claim 15 , wherein the surface of the pad layer is substantially lower than a surface of the passivation layer.