System and method for implementing flow control with dynamic load balancing for single channelized input to multiple outputs
An interface between a high speed data signal input and multiple lower speed data signal outputs is described. In one preferred embodiment, the interface comprises a receiver core for separating the high speed data signal into multiple independent channels with each channel having a different priority; an Interface Logic Unit comprising multiple interface logic subunits each for processing one of the multiple independent channels. Each of the interface logic subunits includes a separator for separating the individual channel into multiple intermediate signals; and feedback device for providing feedback to the receiver core regarding a condition of one or more of the multiple intermediate signals. The interface further includes multiple multiplexer with each receiving one of the multiple intermediate signals and multiplexing the received intermediate signals to create one of the multiple lower speed data signals.
1. An interface between a data signal input and N data signal outputs, the interface comprising:
a receiver core for separating the data signal input into M individual channels each channel having a different priority for each N data signal output having a different rate and different priority;
an Interface Logic Unit (“ILU”) comprising M interface logic subunits each for processing one of the M individual channels and each comprising:
means for separating at least one of the M individual channels into N intermediate signals;
means for providing feedback to the receiver core regarding a condition of one or more of the N intermediate signals;
means for generating control signals responsive to an error packet or an end of packet in one or more of the M individual channels;
means for implementing load balancing among one or more of the N intermediate signals;
means for implementing load balancing among the N data signal outputs; and
a multiplexer unit comprising N multiplexers (“MUXes”) each receiving one of the N intermediate signals from each of M interface logic subunits and multiplexing the received intermediate signals to create one of the N lower speed data signals.
2. The interface of claim 1 wherein each of the intermediate signals received at a MUX has a different priority.
3. The interface of claim 1 wherein the priority of the at least one of the M individual channels is selected from a group consisting of a first priority, a second priority, a third priority, and a fourth priority.
4. The interface of claim 1 wherein the feedback to the receiver core regards whether one or more of the N intermediate signals needs flow control.
5. The interface of claim 1 wherein the feedback to the receiver core regards whether a need exists to implement a dynamic load balancing between the N intermediate signals and the M individual channels.
6. The interface of claim 1 wherein each of the M interface logic subunits comprises:
a first FIFO that receives one of the M individual channels; and
N FIFOs for each receiving one of the N intermediate signals and providing a feedback signal to the means for separating on a status of at least one of the N FIFO as FULL or NOT FULL wherein the parser implement load balancing between the N FIFOs in response to the feedback signal and signals the receiver core to implement load balancing between the N lower speed data signal outputs.
7. The interface of claim 6 wherein the means for separating comprises a HASH function for implementing load balancing between the N FIFOs, the HASH function for implementing a HASH algorithm selected from a plurality of HASH algorithms based on the status of the N FIFOs.
8. The interface of claim 6 wherein each of the interface logic subunits further comprises:
a control FIFO connected to the input of the first FIFO and to the means for separating, wherein the control FIFO provides a signal to the means for separating in response to an error packet or end-of-packet in the first FIFO; and
wherein the parser drops a packet in response to receipt of the signal from the control FIFO.
9. The interface of claim 8 wherein each of the N MUXes prioritizes receipt and output of the N intermediate signals from the interface logic subunits by priority of the M channels to the different interface logic subunits.
10. An interface between a data signal input and N data signal outputs, the interface comprising:
receiver means for separating the data signal input into M individual channels each channel having a different priority for each N data signal output having a different rate and different priority;
interface means comprising M subunits each for processing one of the M individual channels and each comprising:
means for separating at least one of the M individual channels into N intermediate signals;
means for providing feedback to the receiver means regarding a condition of one or more of the N intermediate signals;
means for generating control signals responsive to an error packet or an end of packet in one the at least of the M individual channels;
means for implementing load balancing among one or more of the N intermediate signals;
means for implementing load balancing among the N data signal outputs by the receiver means; and
N multiplexer (“MUX”) means each for receiving one of the N intermediate signals from each of the M subunits and multiplexing the received intermediate signals to create one of the N lower speed data signals.
11. The interface of claim 10 wherein each of the intermediate signals received at one of the N MUX means has a different priority.
12. The interface of claim 10 wherein the priority of the at least one of the M individual channels is selected from a group consisting of a first priority, a second priority, a third priority, and a fourth priority.
13. The interface of claim 10 wherein the feedback to the receiver means indicates whether one or more of the N intermediate signals needs flow control.
14. The interface of claim 10 wherein the feedback to the receiver means indicates whether a need exists to implement a dynamic load balancing between the N intermediate signals and the M individual channels.
15. The interface of claim 10 wherein each of the M subunits comprises:
first means for receiving the at least one of the M individual channels;
N second means each for receiving one of the N intermediate signals and providing a feedback signal to the means for separating concerning a status of the at least one of the N second means for receiving as FULL or NOT FULL;
control means connected to the input of the first means for receiving and to the means for separating, for providing a signal to the means for separating in response to an error packet or end-of-packet in the first means; and.
16. The interface of claim 15 wherein the means for separating comprises means for implementing a HASH algorithm for implementing load balancing between the N second means for receiving, wherein the HASH algorithm is selected from a plurality of HASH algorithms based on the status of the N second means for receiving.
17. The interface of claim 15 wherein the first means for receiving comprises a FIFO.
18. The interface of claim 15 wherein the means for separating comprises a parser.
19. The interface of claim 15 wherein each of the N second means for receiving comprises a FIFO.
20. The interface of claim 15 wherein the control means comprises a control FIFO.
21. The interface of claim 15 wherein the means for separating drops a packet in response to receipt of the signal from the control means.
22. A method of providing an interface between a data signal input and N data signal outputs, the method comprising:
separating the data signal input into M individual channels each channel having a different priority for each N data signal output having a different rate and different priority;
processing each of the M individual channels by:
separating at least one of M individual channels into N intermediate signals; and
providing feedback to a receiver core regarding a condition of one or more of the N intermediate signals;
receiving at each of N multiplexers (“MUXes”) one of the N intermediate signals from each of M interface logic subunit means, wherein each of the received intermediate signals has a different priority;
generating control signals responsive to an error packet or an end of packet in one or more of the M individual channels;
implementing load balancing among one or more of the N intermediate signals;
implementing load balancing among the N data signal outputs; and
multiplexing the received intermediate signals to create one of the N lower speed data signals.
23. The method of claim 22 further comprising:
providing feedback to the receiver core indicative of whether one or more of the N intermediate signals needs flow control.
24. The method of claim 22 further comprising:
providing feedback to the receiver core indicative of whether a need exists to implement a dynamic load balancing between the N intermediate signals and the M individual channels.
25. The method of claim 22 wherein the processing each of the M interface logic subunit comprises:
receiving at least one of the M channels at a first FIFO;
receiving one of the N intermediate signals at one of N second FIFOs and generating a feedback signal indicative of a status of at least one of the N second FIFOs for receiving as FULL or NOT FULL;
generating a control signal in response to an error packet or end-of-packet in the first FIFO;
implementing load balancing between N second FIFOs second means for receiving in response to the feedback signal; and
signaling the receiver core to implement load balancing between N lower speed data signal outputs.
26. The method of claim 25 further comprising wherein the implementing load balancing comprises executing a HASH algorithm selected from a plurality of HASH algorithms based on the status of the N second FIFOs.
27. The method of claim 25 further comprising dropping a packet in response to receipt of the control signal.
28. The method of claim 27 further comprising prioritizing receipt and output of the N intermediate signals by priority of the corresponding M individual channels.