IP Library › Granted Patent US 7,768,008
Granted Patent B2
US 7,768,008 · App. 11/985,235 · Granted Aug 3, 2010

Thin film transistor, method for manufacturing the same and display using the same

Assignee: Toppan Printing Co., Ltd.
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Quick Facts
Patent No.
US 7,768,008
App. No.
11/985,235
Granted
Aug 3, 2010
Kind
B2
Abstract

One embodiment of the present invention is a thin film transistor including a gate electrode formed on an insulating substrate, a gate insulator formed on the gate electrode, a drain electrode and a source electrode formed on the gate insulator, an oxide semiconductor pattern formed between the drain electrode and the source electrode, and a sealing layer formed on the oxide semiconductor pattern.

Claims (32)

1. A thin film transistor, comprising:

a gate electrode formed on an insulating substrate;

a gate insulator formed on said gate electrode;

an oxide semiconductor pattern formed on said gate insulator;

a sealing layer formed on said oxide semiconductor pattern and said gate insulator; and

a drain electrode and a source electrode formed on said sealing layer; wherein

said sealing layer does not cover a connection part of said source electrode, a connection part of said drain electrode and a connection part of said gate electrode; and wherein said drain electrode and said source electrode are connected to said oxide semiconductor pattern via said connection part of said drain electrode and said connection part of said source electrode.

2. The thin film transistor according to claim 1 ,

wherein said sealing layer is an inorganic insulating film.

3. The thin film transistor according to claim 2 ,

wherein said sealing layer is made of oxide nitride silicon.

4. The thin film transistor according to claim 1 ,

wherein said sealing layer is a fluorinated polymer.

5. The thin film transistor according to claim 1 , further comprising:

a gate wire connected to said gate electrode;

a capacitor electrode;

a capacitor wire connected to said capacitor electrode, wherein said gate wire, said capacitor electrode and said capacitor wire are in the same layer as said gate electrode;

a drain wire connected to said drain electrode; and

a pixel electrode connected to said source electrode, said drain wire and said pixel electrode being in the same layer as said drain electrode and said source electrode, wherein

said sealing layer covers said oxide semiconductor pattern and said gate insulator other than said connection part of said source electrode, said connection part of said drain electrode and a part of said pixel electrode under which said capacitor electrode is formed, wherein

said drain electrode and said source electrode are connected to said oxide semiconductor pattern via said connection part of said drain electrode and said connection part of said source electrode,

and wherein said sealing layer is not formed over said pixel electrode.

6. The thin film transistor according to claim 1 , further comprising:

a gate wire connected to said gate electrode;

a capacitor electrode;

a capacitor wire connected to said capacitor electrode, wherein said gate wire, said capacitor electrode and said capacitor wire are in the same layer as said gate electrode;

a drain wire connected to said drain electrode; and

a pixel electrode connected to said source electrode, said drain wire and said pixel electrode being in the same layer as said drain electrode and said source electrode,

wherein said sealing layer covers said oxide semiconductor pattern and said gate insulator other than said connection part of said source electrode, said connection part of said drain electrode and a part of said pixel electrode under which said capacitor electrode is formed, and

wherein said drain electrode and said source electrode are connected to said oxide semiconductor pattern via said connection part of said drain electrode and said connection part of said source electrode,

wherein an interlayer dielectric having an opening on the pixel electrode is formed on the sealing layer, and

wherein an upper pixel electrode connected to the pixel electrode through the opening is formed on the interlayer dielectric.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2007
From: ISHIZAKI, MAMORU; ITO, MANABU; KON, MASATO; KINA, OSAMU; MATSUBARA, RYOHEI
To: TOPPAN PRINTING CO., LTD.
Reel/Frame 020162/0980 →
Continuity (1)
Related Publication 20090121225A1 · May 14, 2009