Semiconductor structure and method of manufacture
In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.
1. A structure, comprising:
a first dielectric material and a first void below a surface of a substrate; and
a doped dielectric material over the first dielectric material, over the first void, wherein at least a portion of the first dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material.
2. The structure of claim 1 , wherein the substrate is a semiconductor substrate.
3. The structure of claim 1 , wherein the first void abuts the first dielectric material and abuts the doped dielectric material.
4. The structure of claim 1 , further comprising a second void below the surface of the substrate and isolated from the first void, wherein the first void abuts the doped dielectric material and the second void abuts the doped dielectric material.
5. The semiconductor structure of claim 1 , wherein the doped dielectric material is above the surface of the substrate.
6. The structure of claim 1 , further comprising an electrically conductive material over the doped dielectric material and over the surface of the substrate.
7. The structure of claim 6 , wherein the electrically conductive material comprises aluminum, copper, doped polycrystalline silicon, gold, nickel, or permalloy, or combinations thereof, and wherein the substrate comprises silicon.
8. The structure of claim 6 , further comprising an active device, wherein a portion of the active device is formed in the substrate adjacent to the first dielectric material.
9. The structure of claim 8 , wherein the active device is a field effect transistor (FET) having a gate, a gate oxide, a source region, a drain region, and a channel region, and the portion of the active device is the source region, the channel region, or the drain region of the FET.
10. The structure of claim 8 , further comprising a passive device, wherein the passive device comprises the electrically conductive layer and wherein the electrically conductive layer is coupled to the active device.
11. The structure of claim 10 , wherein the passive device is an inductor, a capacitor, or an interconnect, or combinations thereof.
12. The structure of claim 1 , further comprising a second dielectric material over the doped dielectric material.
13. The structure of claim 12 , wherein the second dielectric material comprises silicon nitride.
14. The structure of claim 1 , wherein the doped dielectric material is a silicate glass.
15. The structure of claim 14 , wherein the silicate glass comprises boron or phosphorous, or combinations thereof.
16. The structure of claim 1 , wherein the doped dielectric material is phosphorus silicate glass (PSG), boron silicate glass (BSG), or boron phosphorus silicate glass (BPSG), or combinations thereof.
17. The structure of claim 1 , wherein the doped dielectric material comprises an oxide.
18. The structure of claim 17 , wherein the oxide is doped with an impurity material.
19. The structure of claim 18 , wherein the impurity material is boron or phosphorous, or combinations thereof.
20. The structure of claim 1 , wherein the doped dielectric material seals the first void.
21. The structure of claim 1 , wherein the doped dielectric material covers the first void.
22. The structure of claim 1 , wherein the doped dielectric material caps the first void.