Tiled memory array for full search motion estimation

1. An apparatus comprising:

a plurality of memory circuits configured to store a plurality of pixels used in a motion estimation stage of a video encoder, wherein said plurality of memory circuits comprise a search memory;

a plurality of address calculation circuits configured to control addressing to said plurality of memory circuits; and

a logic circuit configured to (i) control which of said pixels are stored in which of said plurality of memory circuits and (ii) control accessing of said plurality of pixels, wherein (a) said logic circuit controls access to said plurality of memory circuits in response to an address signal and a directional signal received from a search controller circuit, (b) said directional signal selects a first search direction for accessing said plurality of pixels in said plurality of memory circuits to the (A) right, (B) left, (C) above, or (D) below a current pixel, (c) said directional signal selects a second search direction for accessing said plurality of pixels in said plurality of memory circuits to the (A) right, (B) left, (C) above, or (D) below said current pixel, (d) said first search direction is different from said second search direction, and (e) said second search direction is selected after completion of accessing said plurality of pixels in said first search direction.

2. The apparatus according to claim 1 , wherein said logic circuit further comprises:

a first shift circuit configured to shift data from said plurality of memory circuits; and

a second shift circuit configured to shift data to said plurality of memory circuits.

3. The apparatus according to claim 1 , wherein said pixels stored in said plurality of memory circuits presented to a motion estimation processing element array.

4. The apparatus according to claim 1 , wherein each of said plurality of memory circuits comprises a bank of random access memory (RAM).

5. The apparatus according to claim 2 , wherein said pixels are stored in said plurality of memory circuits in a pattern that allows simultaneous access to each of said pixels.

6. The apparatus according to claim 1 , wherein said pixels are stored and accessed in groups of line segments comprising a plurality of said pixels.

7. The apparatus according to claim 6 , wherein said apparatus allows directional access to said line segments, in response to a said direction signal from said logic circuit.

8. The apparatus according to claim 6 , wherein said apparatus stores a plurality of said line segments that are accessed in one of a plurality of search patterns.

9. An apparatus comprising:

means for storing a plurality of pixels in a plurality of memory banks, wherein said pixels are used in a motion estimation stage of a video encoder, wherein said plurality of memory banks comprise a search memory; and

means for calculation of address locations to control addressing to said plurality of memory banks; and

means for controlling which of said pixels are stored in which of said plurality of memory banks with a logic circuit; and

means for accessing said plurality of pixels in response to said logic circuit, wherein (a) said logic circuit controls access to said plurality of memory banks in response to an address signal and a directional signal received from a search controller circuit, (b) said directional signal selects a first search direction for accessing said plurality of pixels in said plurality of memory banks to the (A) right, (B) left, (C) above, or (D) below a current pixel, (c) said directional signal selects a second search direction for accessing said plurality of pixels in said plurality of memory banks to the (A) right, (B) left, (C) above, or (D) below said current pixel, (d) said first search direction is different from said second search direction, and (e) said second search direction is selected after completion of accessing said plurality of pixels in said first search direction.

10. A method for storing search data, comprising the steps of:

(A) storing a plurality of pixels in a plurality of memory banks, wherein said pixels are used in a motion estimation stage of a video encoder, wherein said plurality of memory banks comprise a search memory;

(B) calculating addresses to said plurality of memory banks using a plurality of address calculation circuits; and

(C) controlling which of said pixels are stored in which of said plurality of memory banks with a logic circuit; and

(D) accessing said plurality of pixels in response to said logic circuit, wherein (i) said logic circuit controls access to said plurality of memory banks in response to an address signal and a directional signal received from a search controller circuit, (ii) said directional signal selects a first search direction for accessing said plurality of pixels in said plurality of memory banks to the (a) right, (b) left, (c) above, or (d) below a current pixel, (iii) said directional signal selects a second search direction for accessing said plurality of pixels in said plurality of memory banks to the (a) right, (b) left, (c) above, or (d) below said current pixel, (iv) said first search direction is different from said second search direction, and (v) said second search direction is selected after completion of accessing said plurality of pixels in said first search direction.

11. The method according to claim 10 , wherein said logic circuit further comprises:

a first shift circuit configured to shift data from said plurality of memory banks; and

a second shift circuit configured to shift data to said plurality of memory banks.

12. The method according to claim 10 , wherein said pixels stored in said plurality of memory banks presented to a motion estimation processing element array.

13. The method according to claim 10 , wherein said pixels are stored and accessed in groups of line segments comprising a plurality of said pixels.

14. The method according to claim 13 , wherein said method allows directional access to said line segments, in response to a direction signal from said logic circuit.

15. The method according to claim 13 , wherein said method stores a plurality of said line segments that are accessed in one of a plurality of search patterns.