Memory devices with error detection using read/write comparisons

1. A memory device comprising:

a main memory cell array;

a redundant memory cell array configured to store a first parity code for data stored in the main memory cell array;

a first parity generator configured to generate the first parity code responsive to input of the data to the main memory cell array;

a second parity generator configured to generate a second parity code responsive to reading of the stored data from the main memory cell array during a copyback operation; and

a comparator configured to compare the first and second parity codes.

2. The memory device of claim 1 , wherein the main memory cell array and the redundant memory cell array comprise NAND flash memory cell arrays.

3. The memory device of claim 1 , further comprising a repair memory cell array configured for repair of the redundant memory cell array.

4. The memory device of claim 3 , wherein the repair memory cell array has the same cell configuration as the redundant memory cell array.

5. The memory device of claim 3 , further comprising means for selecting the redundant memory cell array or the repair memory cell array.

6. The memory device of claim 5 , wherein the selecting means comprises a fuse circuit.

7. The memory device of claim 1 , wherein each of the first and second parity codes is a one-bit parity code.

8. The memory device of claim 1 , wherein the main memory cell array is divided into a plurality of memory cell arrays.

9. The memory device of claim 8 , wherein the first and second parity codes comprise parity codes having the same number of bits as the number of the plurality of memory cell arrays.

10. A memory device comprising:

a memory cell array;

a first parity generator configured to generate a first parity code responsive to input of data to the memory cell array;

a second parity generator configured to generate a second parity code responsive to output of data from the memory cell array; and

a comparator configured to compare the first and second parity codes,

wherein the memory cell array comprises a main memory cell array, and further comprising a redundant memory cell array configured to store the first parity code.

11. The memory device of claim 10 , wherein the memory cell array comprises a NAND flash memory cell array.

12. The memory device of claim 11 , wherein the second parity generator is configured to generate the second parity code responsive to a copyback operation.

13. The memory device of claim 10 , wherein the first and second parity codes are each 1-bit parity codes.

14. The memory device of claim 10 , wherein the main memory cell array comprises a plurality of memory cell arrays.

15. The memory device of claim 10 , wherein the first and second parity codes have the same number of bits as the number of the plurality of memory cell arrays.

16. A method for detecting errors in an integrated circuit memory device, comprising the following operations performed in the integrated circuit memory device:

generating a first parity code in the integrated circuit memory device responsive to input of data to be written to a memory cell array of the memory device;

generating a second parity code in the integrated circuit memory device responsive to reading of the data from the memory cell array; and

comparing the first and second parity codes in the integrated circuit memory device to detect an error.

17. The method of claim 16 , wherein the memory device is a NAND flash memory device.

18. The method of claim 17 , wherein generating a second parity code comprises generating the second parity code responsive to a copyback operation.

19. The method of claim 16 , wherein generating the first parity code comprises generating the first parity code using a first parity generator, and wherein the method further comprises:

storing the data to be written to the memory cell array in the memory cell array; and

storing the first parity code in a redundant memory cell array of the memory device.

20. The method of claim 19 , further comprising repairing the redundant memory cell array.

21. The method of claim 19 , wherein generating the second parity code comprises:

reading the written data from the memory cell array; and

generating the second parity code from the read data using a second parity generator.

22. The method of claim 21 , where comparing the first and second parity codes comprises:

reading the first parity code from the redundant memory cell array; and

comparing the first and second parity codes.

23. The method of claim 16 , wherein the memory cell array comprises a plurality of memory cell arrays, and wherein the first and second parity codes have the same number of bits as the number of the plurality of memory cell arrays.