Method for producing a layer arrangement
The invention relates to a method for producing a layer arrangement. An electrically conductive layer is formed and patterned. A sacrificial layer formed on at least part of the patterned electrically conductive layer. An electrically insulating layer is formed on the electrically conductive and sacrificial layers and is patterned in such a manner that one or more surface areas of the sacrificial layer are exposed. The exposed areas of the sacrificial layer are removed to expose one or more surface areas of the patterned electrically conductive layer. The patterned electrically conductive layer is covered with a pattern of electrically conductive material.
1. A method for manufacturing a layer arrangement, comprising:
forming an electrically conductive layer on a substrate, the electrically conductive layer comprising an upper end section;
patterning the electrically conductive layer to form a patterned electrically conductive layer;
forming a sacrificial layer on a part of the patterned electrically conductive layer, the sacrificial layer having a first thickness;
forming an electrically insulating layer on the electrically conductive layer and on the sacrificial layer, the electrically insulating layer having a second thickness and a thickness variation range;
patterning the electrically insulating layer to expose a surface area of the sacrificial layer;
removing an exposed area of the sacrificial layer to expose the patterned electrically conductive layer; and
covering the patterned electrically conductive layer with a pattern of electrically conductive material;
wherein the first thickness is at least as large as the thickness variation range of the electrically insulating layer.
2. The method of claim 1 , further comprising using the sacrificial layer as a stop layer.
3. The method of claim 1 , where patterning the electrically insulating layer comprises removing the electrically insulating layer until the surface area of the sacrificial layer on the upper end section of the electrically conductive layer is reached.
4. The method of claim 3 , where the exposed area of the sacrificial layer and the electrically insulating layer are removed using an etching process.
5. The method of claim 4 , further comprising using at least one of tetrafluoromethane, trifluoromethane, nitrogen, and argon as an etchant in the etching process.
6. The method of claim 4 , further comprising adjusting a concentration of carbon monoxide in an etchant to adjust an etching rate of the etching process.
7. The method of claim 4 , further comprising adjusting a concentration of at least one of oxygen and hydrogen in an etchant to adjust an etching rate of the etching process.
8. The method of claim 1 , where the first thickness is less than the second thickness.
9. The method of claim 1 , further comprising forming a liner layer between the electrically conductive layer and the pattern of electrically conductive material.
10. The method of claim 9 , where the liner layer is formed after removing the exposed area of the sacrificial layer to expose the patterned electrically conductive layer.
11. The method of claim 9 , where the liner layer is formed from titanium nitride.
12. The method of claim 1 , where patterning the electrically conductive layer comprises using a lithography process and an etching process.
13. The method of claim 1 , where forming the sacrificial layer comprises using a conformal deposition process.
14. The method of claim 1 , where the layer arrangement comprises an integrated circuit.
15. The method of claim 1 , further comprising forming vias filled with a pattern of electrically conductive material, and where patterning the electrically conductive layer comprises forming conductor tracks through patterning the electrically conductive layer.
16. The method of claim 1 , where the electrically conductive layer is formed from at least one of aluminum and tungsten.
17. The method of claim 1 , where the sacrificial layer is formed from at least one of silicon nitride and silicon oxynitride.
18. The method of claim 1 , where the electrically insulating layer is formed from silicon oxide.
19. The method of claim 3 , where the exposed area of the sacrificial layer is removed at a higher rate than the electrically insulating layer is removed.