Digital implementation of an enhanced minsum algorithm for error correction in data communications

1. An iterative error correcting decoder comprising:

an equality constraint node; and

a parity check node, the parity check node including,

parity logic configured to receive input data bits from the equality constraint node and determine a first minimum value and a second minimum value associated with the input data bits using a MinSum algorithm,

wherein an enhancement function is performed on the first minimum value and the second minimum value, the enhancement function,

comparing each of the first minimum value and the second minimum value with a first pre-determined constant value; and

responsive to the first minimum value and the second minimum value being smaller than the first pre-determined constant value, the enhancement function passes the first minimum value and the second minimum value without any changes as output of the MinSum algorithm.

2. The iterative error correcting decoder of claim 1 , further comprising:

responsive to the first minimum value or the second minimum value being smaller than the first pre-determined constant value, the enhancement function respectively subtracts a second pre-determined value from the first minimum value or the second minimum value prior to passing the first minimum value and the second minimum value as output of the MinSum algorithm.

3. The iterative error correcting decoder of claim 2 , wherein the first minimum value and the second minimum value is in 2's complement format.

4. The iterative error correcting decoder of claim 2 , wherein the iterative error correcting decoder is one of a low density parity check (LDPC) decoder, a Hamming decoder, a Reed-Solomon decoder, or a Turbo decoder.

5. The iterative error correcting decoder of claim 4 , wherein the iterative error correcting decoder is compliant with the IEEE 802.3ae (10 GBASE-T) standard.

6. The iterative error correcting decoder of claim 2 , further comprising variable sum logic to serially pass the input data bits to the parity logic.

7. The iterative error correcting decoder of claim 6 , wherein the variable sum logic serially passes the input data bits to the parity logic with the most significant bits (MSB) first.

8. The iterative error correcting decoder of claim 6 , wherein the variable sum logic comprises a plurality of adders.

9. The iterative error correcting decoder of claim 8 , further comprising a flop implemented between a carry going from a least significant bit (LSB) adder to a next higher adder to reduce an amount of false switching prior to all the data for the next higher adder being ready.