Error correction devices and correction methods
An error correction device is provided. When an error of a data group stored in a dynamic random access memory (DRAM) device is detected, a memory controller of the error correction device executes a burst read and write, burst write or burst read-modify-write (RMW) operations to the DRAM instead of the conventional single read-modify-write (RMW) operation, thereby reducing the occupied bandwidth of the DRAM.
1. An error correction device comprising:
a first memory storing a plurality of data sets;
a reed-solomon (RS) engine receiving a plurality of error correction codes and determining an error sequence according to the error correction codes for modifying an incorrect data group among the plurality of data sets;
a memory controller executing a burst read operation to the first memory to control the first memory to output the data group for modifying;
a computing unit receiving the error sequence from the RS engine and the data group from the first memory and performing a logic operation for the error sequence and the data group to obtain the modified data group; and
a second memory coupled to the computing unit and storing the modified data group;
wherein the memory controller executes a write operation to control the first memory to receive and store the modified data group from the second memory.
2. The error correction device as claimed in claim 1 , wherein the data group comprises a plurality of bytes of data.
3. The error correction device as claimed in claim 1 , wherein the second memory is a first-in, first-out buffer.
4. The error correction device as claimed in claim 1 , wherein the first memory is a synchronous dynamic random access memory (SDRAM).
5. The error correction device as claimed in claim 1 , wherein the logic operation is an exclusive OR operation (XOR).
6. The error correction device as claimed in claim 1 , wherein the memory controller sends one pre-charge command and one active command to the first memory before the burst read operation, and when the memory controller executes the burst read operation, the memory controller sends a plurality of read commands to the first memory.
7. An error correction device, comprising:
a reed-solomon (RS) engine receiving a plurality of error correction codes and determining an error sequence according to the error correction codes;
a first memory storing a plurality of data sets;
a second memory storing an incorrect data group among the plurality of data sets;
a computing unit receiving the error sequence from the RS engine and the data group from the second memory, performing a logic operation for the error sequence and the data group, and then outputting the modified data group to the second memory for storage; and
a memory controller executing a burst write operation on the first memory to control the first memory to receive the modified data group from the second memory for storage.
8. The error correction device as claimed in claim 7 , wherein the data group comprises a plurality of bytes of data.
9. The error correction device as claimed in claim 7 , wherein the second memory is a first-in, first-out buffer.
10. The error correction device as claimed in claim 7 , wherein the first memory is a synchronous dynamic random access memory (SDRAM).
11. The error correction device as claimed in claim 7 , wherein the logic operation is an exclusive OR operation (XOR).
12. An error correction device for correcting n data sets, comprising:
a memory storing the n data sets;
a reed-solomon (RS) engine receiving a plurality of error correction codes and determining n error values according to the error correction codes;
a memory controller executing a burst read-modify-write (RMW) operation to the memory for modifying the n data sets in n predetermined periods; and
a computing unit coupled to the RS engine and the memory controller;
wherein when the memory controller executes the burst RMW operation to the memory, in the i-th predetermined period among the n predetermined periods, the computing unit receives the i-th data set from the memory, performs a logic operation for the i-th data set and the i-th error value to obtain the i-th modified data set, and outputs the i-th modified data set to the memory for storage, 1≦i≦n.
13. The error correction device as claimed in claim 12 , wherein the data group comprises a plurality of bytes of data.
14. The error correction device as claimed in claim 12 , wherein the logic operation is an exclusive OR operation (XOR).
15. A method for correcting a plurality of data sets stored in a first memory, comprising:
determining that a data group among the plurality of data sets stored in the first memory is incorrect;
receiving a plurality of error correction codes;
determining an error sequence according to the error correction codes
executing a burst read operation to the first memory to control the first memory to output the data group for modifying;
performing a logic operation for the error sequence and the data group to get the modified data group;
storing the modified data group in a second memory; and
executing a write operation to control the first memory to store the modified data group from the second memory.
16. The method as claimed in claim 15 , wherein the data group comprises a plurality of bytes of data.
17. The method as claimed in claim 15 , wherein the logic operation is an exclusive OR operation (XOR).
18. A method for correcting a plurality of data sets stored in a first memory, comprising:
determining that a data group among the plurality of data sets stored in the first memory is incorrect;
storing the data group in a second memory
receiving a plurality of error correction codes;
determining an error sequence according to the error correction codes;
reading the data group from the second memory;
performing a logic operation for the error sequence and the data group from second memory to get the modified data group;
outputting the modified data group to the second memory for storage; and
executing a burst write operation to the first memory to control the first memory to store the modified data group from the second memory.
19. The method as claimed in claim 18 , wherein the data group comprises a plurality of bytes of data.
20. The method as claimed in claim 18 , wherein the logic operation is an exclusive OR operation (XOR).
21. The method as claimed in claim 18 further comprising storing the modified data group in the second memory and outputting the modified data group to the first memory.
22. A method for correcting n data sets stored in a memory, comprising:
receiving a plurality of error correction codes;
determining n error values according to the error correction codes;
executing a burst read-modify-write (RMW) operation to the memory to output the n data sets in n predetermined periods for modifying; and
performing a logic operation for the i-th data set and the i-th error value to obtain the i-th modified data set and storing the i-th modified data set to the memory in the i-th predetermined period among the n predetermined periods, wherein 1≦i≦n.
23. The method as claimed in claim 22 , wherein the data group comprises a plurality of bytes of data.
24. The method as claimed in claim 22 , wherein the logic operation is an exclusive OR operation (XOR).