Method of forming a silicide layer while applying a compressive or tensile strain to impurity layers
A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p + ) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×10 19 atoms/cm 3 or more and yet less than or equal to 1×10 21 atoms/cm 3 . Next, silicidize the p + -type layers by reaction with a metal in the state that each layer is applied a compressive strain.
1. A method of making a semiconductor device comprising:
forming a gate insulating film above a semiconductive substrate;
forming a gate electrode on the gate insulating film;
forming in or on the substrate at both sides of the gate electrode a pair of spaced-apart heavily-doped impurity layers of p-type conductivity to a concentration ranging from 5×10 19 to 1×10 21 atoms per cubic centimeter (/cm 3 );
forming a silicide layer by causing the impurity layers to react with a metal while simultaneously applying a compressive strain to the impurity layers; and
forming a Si x Ge 1-x (where x is greater than or equal to zero and less than one) layer in or on the substrate at the both sides of the gate electrode,
wherein the impurity layers are formed at least in a region between the gate electrode and the Si x Ge 1-x layer.
2. The method of claim 1 , further comprising
forming a first sidewall insulator film on both side faces of the gate electrode,
etching the substrate with the gate electrode and the first sidewall insulator film being as a mask,
removing the first sidewall insulator film, and
forming on the both faces of the gate electrode a second sidewall insulator film less in thickness than the first sidewall insulator film after having removed the first sidewall insulator film,
wherein the Si x Ge 1-x layer is formed after etching the substrate and yet prior to removal of the first sidewall insulator film and
wherein the impurity layers are formed by doping an impurity by ion implantation with the gate electrode and the second sidewall insulator film as a mask.
3. The method of claim 1 , further comprising
forming a sidewall insulator film on both side faces of the gate electrode, and
etching the substrate with the gate electrode and the sidewall insulator film as a mask,
wherein the impurity layers are formed after having etched the substrate and
wherein the Si x Ge 1-x layer is formed after having formed the impurity layers.
4. The method of claim 1 , wherein the substrate is a silicon substrate and wherein the impurity is boron (B) whereas the metal is nickel (Ni).
5. A method of making a semiconductor device comprising:
forming a gate insulating film above a semiconductive substrate;
forming a gate electrode on the gate insulating film;
forming in or on the substrate at both sides of the gate electrode a pair of spaced-apart heavily-doped impurity layers of p-type conductivity to a concentration ranging from 5×10 19 to 1×10 21 atoms per cubic centimeter (/cm 3 ); and
forming a silicide layer by causing the impurity layers to react with a metal while simultaneously applying a compressive strain to the impurity layers;
wherein the impurity layers have their lattice constant under application of the compressive strain, the lattice constant being deviated from a lattice constant in a state free from the compressive strain by 0.2 percent (%) or more and less than 1.0% or below.
6. A method of making a semiconductor device comprising:
forming a gate insulating film above a semiconductive substrate;
forming a gate electrode on the gate insulating film;
forming in or on the substrate at both sides of the gate electrode a pair of spaced-apart heavily-doped impurity layers of n-type conductivity to a concentration ranging from 5×10 19 to 1×10 21 atoms per cubic centimeter (/cm 3 );
forming a silicide layer by causing the impurity layers to react with a metal while simultaneously applying a tensile strain to the impurity layers; and
forming a Si x C 1-x (where 0≦×<1) layer in or on the substrate at the both sides of the gate electrode,
wherein the impurity layers are formed in at least a region between the gate electrode and the Si x C 1-x layer.
7. The method of claim 6 , further comprising
forming a first sidewall insulator film on both side faces of the gate electrode,
etching the substrate with the gate electrode and the first sidewall insulator film being as a mask, removing the first sidewall insulator film, and
forming on the both faces of the gate electrode a second sidewall insulator film less in thickness than the first sidewall insulator film after having removed the first sidewall insulator film,
wherein the Si x C 1-x layer is formed after etching the substrate and yet prior to removal of the first sidewall insulator film and
wherein the impurity layers are formed by doping an impurity by ion implantation with the gate electrode and the second sidewall insulator film as a mask.
8. The method of claim 6 , further comprising
forming a sidewall insulator film on both side faces of the gate electrode, and
etching the substrate with the gate electrode and the sidewall insulator film as a mask,
wherein the impurity layers are formed after having etched the substrate and
wherein the Si x C 1-x layer is formed after having formed the impurity layers.
9. The method of claim 6 , wherein the substrate is a silicon substrate and wherein the impurity is arsenic (As) whereas the metal is nickel (Ni).